Efficient improvement of hot carrier-induced degradation for 0.1-mu m indium-halo nMOSFET

doi:10.1109/TED.2004.823797

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DC Field	Value	Language
dc.contributor.author	Yeh, WK	en_US
dc.contributor.author	Lin, JC	en_US
dc.date.accessioned	2014-12-08T15:39:22Z	-
dc.date.available	2014-12-08T15:39:22Z	-
dc.date.issued	2004-04-01	en_US
dc.identifier.issn	0018-9383	en_US
dc.identifier.uri	http://dx.doi.org/10.1109/TED.2004.823797	en_US
dc.identifier.uri	http://hdl.handle.net/11536/26889	-
dc.description.abstract	The effect of post-thermal annealing after indium-halo implantation on the reliability of sub-0.1-mum nMOSFETs was investigated. We found that the control of annealing time is more efficient than that of annealing temperature with respect to improving the hot carrier-induced device degradation. The best results of device performance were obtained with post-annealing treatment performed at medium temperatures (e.g., 900 degreesC) for a longer time.	en_US
dc.language.iso	en_US	en_US
dc.subject	hot carrier-induced device degradation	en_US
dc.subject	indium halo (In-halo)	en_US
dc.subject	post-thermal annealing (PA)	en_US
dc.title	Efficient improvement of hot carrier-induced degradation for 0.1-mu m indium-halo nMOSFET	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1109/TED.2004.823797	en_US
dc.identifier.journal	IEEE TRANSACTIONS ON ELECTRON DEVICES	en_US
dc.citation.volume	51	en_US
dc.citation.issue	4	en_US
dc.citation.spage	642	en_US
dc.citation.epage	644	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000220458000019	-
dc.citation.woscount	0	-
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