標題: A CMOS 33-mW 100-MHz 80-dB SFDR sample-and-hold amplifier
作者: Hsu, CC
Wu, JT
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: sample-and-hold circuits;switched-capacitor circuits;time-interleaved analog-to-digital converter
公開日期: 1-Oct-2003
摘要: A high-speed high-resolution sample-and-hold amplifier (SHA) is designed for time-interleaved analog-to-digital converter applications. Using the techniques of precharging and output capacitor coupling can mitigate the stringent performance requirements for the opamp, resulting in low power dissipation. Implemented in a standard 0.25 mum CMOS technology, the SHA achieves 80 dB spurious-free dynamic range (SFDR) for a 1.8 Vpp output at 100MHz Nyquist sampling rate. The SHA occupies a die area of 0.35 mm(2) and dissipates 33mW from a single 2.5V supply.
URI: http://hdl.handle.net/11536/27463
ISSN: 0916-8524
期刊: IEICE TRANSACTIONS ON ELECTRONICS
Volume: E86C
Issue: 10
起始頁: 2122
結束頁: 2128
Appears in Collections:Articles