標題: | An Area-Efficient Parallel Turbo Decoder Based on Contention Free Algorithm |
作者: | Tseng, Kai-Hsin Chuang, Hsiang-Tsung Tseng, Shao-Yen Fang, Wai-Chi 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 2009 |
摘要: | In this paper, a contention free algorithm for solving memory collision problem of parallel Turbo decoder architecture using the simulated annealing algorithm is presented. Furthermore, we proposed two area-efficient extrinsic memory schemes based on the parallel contention free Turbo decoder. One of the proposed schemes employs only multiple single port memories with one temporary buffer instead of the original dual port or two port memories and the other scheme further employs an additional non-linear extrinsic mapping architecture. The proposed schemes lead to approximately 37% and 46% memory area reduction, respectively, for 16-parallel Turbo decoder in comparison to the conventional dual port memory scheme under the UMC 0.13-mu m CMOS process. |
URI: | http://hdl.handle.net/11536/27987 |
ISBN: | 978-1-4244-2781-9 |
期刊: | 2009 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PROGRAM |
起始頁: | 203 |
結束頁: | 206 |
顯示於類別: | 會議論文 |