標題: High-performance P-channel Schottky-barrier SOI FinFET featuring self-aligned PtSi source/drain and electrical junctions
作者: Lin, HC
Wang, MF
Hou, FJ
Lin, HN
Lu, CY
Liu, JT
Huang, TY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: ambipolar;Schottky barrier;silicon-on-insulator (SOI)
公開日期: 1-Feb-2003
摘要: A simplified and improved Schottky-barrier metal-oxide-semiconductor device featuring a self-aligned offset channel length, PtSi Schottky junction, and reduced oxide thickness underneath the sub-gate was proposed and demonstrated. To alleviate the drawbacks related to the nonself-aligned offset channel length in the original version, a self-aligned offset channel length is achieved in, the new device by forming the silicide source/drain junction self-aligning to the sidewall spacers abutting the gate. This results in not only one mask count saving but also better device performance, as facilitated by, the reduced offset channel length of the self-aligned sidewall spacers. Moreover, the adoption of PtSi for the Schottky junction further improves the on-state current of p-channel operation, while a thinner oxide employed underneath the sub-gate effectively reduces the sub-gate bias needed to form the electrical junction to below 5 V. Significant improvement in on-current as well as leakage current reduction is achieved in the new improved device.
URI: http://dx.doi.org/10.1109/LED.2002.807717
http://hdl.handle.net/11536/28123
ISSN: 0741-3106
DOI: 10.1109/LED.2002.807717
期刊: IEEE ELECTRON DEVICE LETTERS
Volume: 24
Issue: 2
起始頁: 102
結束頁: 104
Appears in Collections:Articles


Files in This Item:

  1. 000182516600017.pdf

If it is a zip file, please download the file and unzip it, then open index.html in a browser to view the full text content.