標題: Design and analysis of on-chip ESD protection circuit with very low input capacitance for high-precision analog applications
作者: Ker, MD
Chen, TY
Wu, CY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: electrostatic discharge (ESD);ESD protection circuit;input capacitance;analog pin
公開日期: 1-Sep-2002
摘要: An ESD protection design is proposed to solve the ESD protection challenge to the analog pins for high-frequency or current-mode applications. By including an efficient power-rails clamp circuit into the analog I/O pin, the device dimension (W/L) of ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (mum/mum) in a 0.35-mum silicided CMOS process, but it can sustain the human-body-model (machine-model) ESD level of up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only similar to1.0 pF (including the bond pad capacitance) for high-frequency applications. A design model to find the optimized layout dimensions and spacings on the input ESD clamp devices has been also developed to keep the total input capacitance almost constant (within 1% variation), even if the analog input signal has a dynamic range of 1 V.
URI: http://dx.doi.org/10.1023/A:1020351709833
http://hdl.handle.net/11536/28544
ISSN: 0925-1030
DOI: 10.1023/A:1020351709833
期刊: ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
Volume: 32
Issue: 3
起始頁: 257
結束頁: 278
Appears in Collections:Conferences Paper


Files in This Item:

  1. 000178096200007.pdf

If it is a zip file, please download the file and unzip it, then open index.html in a browser to view the full text content.