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dc.contributor.authorLo, WCen_US
dc.contributor.authorChang, SJen_US
dc.contributor.authorChang, CYen_US
dc.contributor.authorChao, TSen_US
dc.date.accessioned2014-12-08T15:42:07Z-
dc.date.available2014-12-08T15:42:07Z-
dc.date.issued2002-08-01en_US
dc.identifier.issn0741-3106en_US
dc.identifier.urihttp://dx.doi.org/10.1109/LED.2002.801334en_US
dc.identifier.urihttp://hdl.handle.net/11536/28617-
dc.description.abstractThe effects of different substrate-contact structures (T-gate and H-gate) dynamic threshold voltage silicon-on-insulator (SOI) nMOSFETs (DTMOS) have been investigated. It is found that H-gate structure devices have higher driving current than T-gate under DTMOS-mode operation. This is because H-gate SOI devices have larger body effect factor (gamma), inducing a lager reduction of threshold voltage. Besides, it is found that drain-induced-barrier-lowering (DIBL) is dramatically reduced for both T-gate and H-gate structure devices when devices are operated under DTMOS-mode.en_US
dc.language.isoen_USen_US
dc.subjectdynamic threshold MOS (DTMOS)en_US
dc.subjectH-gateen_US
dc.subjectsilicon-on-insulator (SOI)en_US
dc.subjectT-gateen_US
dc.titleImpacts of gate structure on dynamic threshold SOI nMOSFETsen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/LED.2002.801334en_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.citation.volume23en_US
dc.citation.issue8en_US
dc.citation.spage497en_US
dc.citation.epage499en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000177207300018-
dc.citation.woscount10-
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