標題: Fully process-compatible layout design on bond pad to improve wire bond reliability in CMOS ICs
作者: Ker, MD
Peng, JJ
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: ball shear test;bond pad;bond wire;layout;reliability;TAB;wire pull test
公開日期: 1-六月-2002
摘要: During manufacture of wire bonding in packaged IC products, the breaking of bond wires and the peeling of bond pads occur frequently. The result is open-circuit failure in IC products. There were several prior methods reported to overcome these problems by using additional process flows or special materials. In this paper, a layout method is proposed to improve the bond wire reliability in general CMOS processes. By changing the layout patterns of bond pads, the reliability of bond wires on bond pads can be improved. A set of different layout patterns of bond pads has been drawn and fabricated in a 0.6-mum single-poly triple-metal CMOS process for investigation by the bond wire reliability tests, the ball shear test and the wire pull test. By implementing effective layout patterns on bond pads in packaged IC products, not only the bond wire reliability can be improved, but also the bond pad capacitance can be reduced for high frequency application. The proposed layout method for bond pad design is fully process-compatible to general CMOS processes.
URI: http://dx.doi.org/10.1109/TCAPT.2002.1010022
http://hdl.handle.net/11536/28756
ISSN: 1521-3331
DOI: 10.1109/TCAPT.2002.1010022
期刊: IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES
Volume: 25
Issue: 2
起始頁: 309
結束頁: 316
顯示於類別:期刊論文


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