A silicon nanowire with a Coulomb blockade effect at room temperature

doi:10.1002/1521-4095(20020517)14:10<736

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Hu, SF	en_US
dc.contributor.author	Wong, WZ	en_US
dc.contributor.author	Liu, SS	en_US
dc.contributor.author	Wu, YC	en_US
dc.contributor.author	Sung, CL	en_US
dc.contributor.author	Huang, TY	en_US
dc.contributor.author	Yang, TJ	en_US
dc.date.accessioned	2014-12-08T15:42:23Z	-
dc.date.available	2014-12-08T15:42:23Z	-
dc.date.issued	2002-05-17	en_US
dc.identifier.issn	0935-9648	en_US
dc.identifier.uri	http://hdl.handle.net/11536/28786	-
dc.identifier.uri	http://dx.doi.org/10.1002/1521-4095(20020517)14:10<736	en_US
dc.description.abstract	An extremely narrow and thin silicon wire has been fabricated on a silicon-on-insulator wafer (see Figure). The room-temperature Coulomb blockade effects as well as the influence of a capacitively coupled gate on the transport properties of this conducting silicon quantum wire are studied. The results obtained are encouraging for the application of such wires in single-electron transistors.	en_US
dc.language.iso	en_US	en_US
dc.title	A silicon nanowire with a Coulomb blockade effect at room temperature	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1002/1521-4095(20020517)14:10<736	en_US
dc.identifier.journal	ADVANCED MATERIALS	en_US
dc.citation.volume	14	en_US
dc.citation.issue	10	en_US
dc.citation.spage	736	en_US
dc.citation.epage	+	en_US
dc.contributor.department	電子物理學系	zh_TW
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electrophysics	en_US
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000175933000009	-
dc.citation.woscount	19	-
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