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dc.contributor.authorLu, CWen_US
dc.contributor.authorLee, CLen_US
dc.contributor.authorSu, CCen_US
dc.contributor.authorChen, JEen_US
dc.date.accessioned2014-12-08T15:42:51Z-
dc.date.available2014-12-08T15:42:51Z-
dc.date.issued2002-02-01en_US
dc.identifier.issn0923-8174en_US
dc.identifier.urihttp://dx.doi.org/10.1023/A:1013784124552en_US
dc.identifier.urihttp://hdl.handle.net/11536/29058-
dc.description.abstractIn this work, IDDQ current for the deep sub-micron VLSI in year 2011 is estimated with a statistical approach according to the International Technology Roadmap for Semiconductors 1999 Edition considering process variations and different input vectors. The estimated results show that the standard deviation of the IDDQ current is proportional to the square root of the circuit size and the IDDQ currents of the defect-free and the defective devices, which are of the size up to 1 x 10(7) gates, are still differentiable under the condition of random process deviations and input vectors. Two new IDDQ testing schemes, which detect the defective current based on the two separate IDDQ distributions, are proposed. From the study, it is concluded that IDDQ testing is still applicable for the deep sub-micron VLSI for the next ten years.en_US
dc.language.isoen_USen_US
dc.subjectIDDQ testingen_US
dc.subjectdeep sub-micronen_US
dc.subjectVLSIen_US
dc.titleAnalysis of application of the IDDQ technique to the deep sub-micron VLSI testingen_US
dc.typeArticle; Proceedings Paperen_US
dc.identifier.doi10.1023/A:1013784124552en_US
dc.identifier.journalJOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONSen_US
dc.citation.volume18en_US
dc.citation.issue1en_US
dc.citation.spage89en_US
dc.citation.epage97en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000173270800010-
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