Reduction of source/drain series resistance and its impact on device performance for PMOS transistors with raised Si1-xGex source/drain

Abstract

P-channel MOS transistors with raised Si1-xGex and Si source/drain (S/D) structure selectively grown by ultra high vacuum chemical vapor deposition (UHVCVD) were fabricated for the first time. The impacts of Si1-xGex and Si epitaxial S/D layer on SID series resistance and drain current of p-channel transistors were studied. Our result show that the new device with Si1-xGex raised S/D layer depicts only half the value of the specific contact resistivity and S/D series resistance (R-SD), compared to the device with Si raised S/D layer. The improvement is even more dramatic, when comparing to the conventional device without any raised Sin layer i.e., R-SD of the new device with Si1-xGex raised S/D is only about one fourth the value of the conventional device. Moreover, the device with raised SiGe S/D structure produces a 29% improvement in transconductance (g(m)) at an effective channel length of 0.16 mu m, These performance improvements, together with several inherent advantages such as self-aligned selective epitaxial growth (SEG) nature and the resultant T-shaped gate structure, make the new device with raised Si1-xGex S/D structure very attractive for future sub-0.1 mu m p-channel MOS transistors.