ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications

標題:	ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications
作者:	Ker, MD Chen, TY Wu, CY Chang, HH 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics
關鍵字:	analog pin;electrostatic discharge;ESD;input capacitance;on-chip ESD protection circuit
公開日期:	1-八月-2000
摘要:	An electrostatic discharge (ESD) protection design is proposed to solve the ESD protection challenge to the analog pins for high-frequency or current-mode applications. By including an efficient power-rails clamp circuit into the analog input/output (I/O) pin, the device dimension (W/L) of an ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (mu m/mu m) in a 0.35-mu m silicided CMOS process, but it can sustain the human body model (HBM) and machine model (MM) ESD level of up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only similar to 1.0 pF (including the bond-pad capacitance) for high-frequency applications.
URI:	http://dx.doi.org/10.1109/4.859509 http://hdl.handle.net/11536/30351
ISSN:	0018-9200
DOI:	10.1109/4.859509
期刊:	IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume:	35
Issue:	8
起始頁:	1194
結束頁:	1199
顯示於類別：	期刊論文

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