標題: Measurement on Snapback Holding Voltage of High-Voltage LDMOS for Latch-up Consideration
作者: Chen, Wen-Yi
Ker, Ming-Dou
Huang, Yeh-Jen
Jou, Yeh-Ning
Lin, Geeng-Lih
電機學院
College of Electrical and Computer Engineering
公開日期: 2008
摘要: In high voltage (HV) ICs, the latch-up immunity of HV devices is often referred to the TLP-measured holding voltage because the huge power generated from DC curve tracer can easily damage HV device during measurement. An n-channel lateral DMOS (LDMOS) was fabricated in a 0.25-mu m 18-V bipolar CMOS DMOS (BCD) process to investigate the validity of TLP-measured snapback holding voltage to the device immunity against latch-up. Experimental results from curve tracer measurement and transient latch-up test show that 100-ns TLP underestimates the latch-up susceptibility of the 18-V LDMOS. By using the long-pulse TLP measurement, snapback holding voltage of the HV device has been found to degrade over time due to the self-heating effect. As a result, since the latch-up event is a reliability test with the time duration longer than millisecond, TLP measurement is not suitable for applying to investigate the snapback holding voltage of HV devices for latch-up.
URI: http://hdl.handle.net/11536/31820
ISBN: 978-1-4244-2341-5
期刊: 2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2008), VOLS 1-4
起始頁: 61
結束頁: 64
顯示於類別:會議論文