Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Jiang, Iris Hui-Ru | en_US |
dc.contributor.author | Wu, Ming-Hua | en_US |
dc.date.accessioned | 2014-12-08T15:47:56Z | - |
dc.date.available | 2014-12-08T15:47:56Z | - |
dc.date.issued | 2008 | en_US |
dc.identifier.isbn | 978-1-4244-2657-7 | en_US |
dc.identifier.issn | 1063-6404 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/32009 | - |
dc.identifier.uri | http://dx.doi.org/10.1109/ICCD.2008.4751835 | en_US |
dc.description.abstract | Interconnect delay and low power are two of the main issues in nano technology. Buffer insertion during routing effectively reduces interconnect delay; power state management and multiple supply voltage significantly lower power consumption. However, buffering without considering power states in multiple supply voltage designs may cause the signal integrity problem. This paper first considers power states into buffered tree construction. Based on a hierarchical approach combined with dynamic programming, we can simultaneously minimize power, satisfy timing constraints and maintain signal integrity. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Power-State-Aware Buffered Tree Construction | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/ICCD.2008.4751835 | en_US |
dc.identifier.journal | 2008 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN | en_US |
dc.citation.spage | 21 | en_US |
dc.citation.epage | 26 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000266685600004 | - |
Appears in Collections: | Conferences Paper |
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