A 2-CHIP 1.5-GBD SERIAL LINK INTERFACE

Abstract

A silicon bipolar transmitter and receiver chip pair transfers parallel data across a 1.5-GBd serial link. A new "conditional-invert master transition" code and phase-locked loop are described and analyzed that provide adjustment-free clock recovery and frame synchronization. The packaged parts require no external components and operate over a range of 700 to 1500 MHz using an on-chip VCO. The line code and handshake protocol have been accepted by the Serial-HIPPI implementor's group for serially transmitting 800-Mb/s HIPPI data, an ANSI standard, and by SCI-FI, an IEEE standard for interconnecting cooperating computers.