完整後設資料紀錄
DC 欄位語言
dc.contributor.authorSu, JGen_US
dc.contributor.authorWong, SCen_US
dc.contributor.authorHuang, CTen_US
dc.date.accessioned2014-12-08T15:48:46Z-
dc.date.available2014-12-08T15:48:46Z-
dc.date.issued1998-09-01en_US
dc.identifier.issn0026-2714en_US
dc.identifier.urihttp://hdl.handle.net/11536/32433-
dc.description.abstractThe Halo structure is usually adopted in deep submicrometer MOS devices for punchthrough prevention. The tilt angle of the Halo implant determines the dopant distribution which induces anti-punchthrough operation. In this paper, we investigate the impact of the tilt angle on the Halo PMOS device performance via two-dimensional (2D) simulations. We find that the ratio of on-current to off-current is constant for all tilt angles of Halo implant, implying an equivalent DC performance for all tilt angles. The equivalence can be traced back to a self compensation between the body factor and source resistance. The result :implies that a low tilt angle should be adopted for Halo devices, for it gives a small threshold voltage and thus a high noise margin. The methodology used in analyzing body factor and source resistance can also be applied to analyze other devices. (C) 1998 Elsevier Science Ltd. All rights reserved.en_US
dc.language.isoen_USen_US
dc.titleA study of tilt angle effect on Halo PMOS performanceen_US
dc.typeArticleen_US
dc.identifier.journalMICROELECTRONICS AND RELIABILITYen_US
dc.citation.volume38en_US
dc.citation.issue9en_US
dc.citation.spage1503en_US
dc.citation.epage1512en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000077017500019-
dc.citation.woscount4-
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