New insight into the degradation mechanism of nitride spacer with different post-oxide in submicron LDD n-MOSFET's

Abstract

In this paper, the hot carrier degradation mechanisms in lightly-doped drain (LDD) n-MOS devices with silicon nitride spacer have been investigated. A low temperature chemical vapor deposited (CVD) SiO2 oxide is used as a post-oxide between source/drain surface and the nitride spacer. The gated-diode measurement in combination with the gate-induced drain leakage (GIDL) current measurement techniques have been used to analyze the stress-induced interface state and oxide charges. For the first time, it was found that the oxide charge but not the interface state generation in the post oxide will dominate the device drain current degradation. Moreover, the CVD post oxide with N-2 annealing has been proposed which is able to effectively suppress the generation of oxide charges and significantly improve the device hot carrier reliability. The scaling of gate oxide thickness and the optimization of source/drain junction to improve the device reliability are also demonstrated.