修正蕭基位障電晶體之源極/汲極阻抗分析

Abstract

隨著電晶體持續微縮至奈米等級，傳統式電晶體面臨許多挑戰，而蕭基位障電晶體具有較為優異的微縮表現，但蕭基位障電晶體受限於其蕭基位障而降低導通電流，修正蕭基位障電晶體可有效的改善其問題。本論文利用元件模擬軟體研究修正蕭基位障電晶體其參數對於元件特性之影響，並且對於源極/汲極阻抗進行最佳化之討論。 本論文利用元件模擬分析修正蕭基位障參數對於修正蕭基位障電晶體之影響。結果發現修正蕭基位障電晶體可分為兩類：一為偏向傳統電晶體之特性，另一為偏向蕭基位障電晶體之特性。偏向傳統電晶體特性之元件具有高濃度或較厚的修正蕭基位障區域，可有效的縮小源極端的蕭基位障之厚度進而增加電子穿隧機率，故元件特性由通道阻抗主導。另一偏向蕭基位障電晶體特性之元件具有較低濃度或較薄的修正蕭基位障區域，故當閘極電壓增加時，此區域容易被閘極電壓空乏而無法達到其作用，故其特性仍受限於源極端的蕭基位障。而當元件持續微縮之下，過厚的修正蕭基位障區域會造成等效元件通道降低的效應，反而造成較嚴重的短通道效應。故當元件微縮後，修正蕭基位障區域必須朝著高濃度薄厚度以達到較好的元件特性。另一所需考慮之特性為DIBL（Drain induced barrier lowering），當修正蕭基位障區域濃度增加時，DIBL現象也會隨之增加。對於通道長度為32 nm之元件，所得到最適當的條件為當修正蕭基位障區域之濃度為3×1019cm-3、厚度為3 nm。 源極/汲極阻抗中，接觸阻抗佔了最重要的部份，利用修正蕭基位障區域提高接觸面之介面濃度，並改變不同的金屬矽化物厚度以增加接觸面積來達到降低阻抗之作用。對於偏向傳統電晶體之元件，其最佳化條件是約金屬矽化物佔矽晶層厚度一半；而偏向蕭基位障電晶體之元件，金屬矽化物愈薄其阻抗愈小，由於其側接面幾乎只有通道表面會有電子穿隧電流，故隨著金屬矽化物厚度增加並不會增加側面之穿隧電流。對於三閘極 (Tri-gate) 電晶體的接觸阻抗，包含兩種源極/汲極金屬矽化物接面：一為平面式，另一為包覆式接觸。平面式最佳化條件趨近於完全金屬矽化之源極/汲極結構，主要受到側面通道之影響。另一包覆式結構最佳化在鰭狀結構寬度為四分之一處。然而，導通電流與及次臨界擺幅的趨勢相同，故元件設計時，必須考慮兩者的權衡關係以得到最適當的元件特性。 本論文採用外部阻抗粹取串聯阻抗之方法（external loading method）於模擬與實際製作的SOI元件。結果發現，對於偏向傳統元件特性之元件可適用此方法，但對於偏向蕭基位障電晶體則無法適用。模擬元件所得到的外部阻抗為160.01 Ω-μm 且其接觸阻抗約為5.5×10-8 Ω-cm2（可達到ITRS標準）。然而，在實際元件中，外部阻抗約為1∼3 kΩ-μm，接觸阻抗約為 6×10-7 Ω-cm2, 相較於模擬結果約大了10倍，主要原因應為其修正蕭基位障區域之濃度並不如預期之高，但元件特性仍是呈現偏向於傳統電晶體之特性，推測為其修正蕭基位障區域之厚度約至10 nm 所致。藉由實際元件與模擬元件之結果可相互比較以推測實際元件之修正蕭基位障區域參數，並且可藉此探討後續實驗之改善條件。

As CMOS device scaling to nanometer regime, the conventional device would meet many challenges to scaling. The Schottky barrier (SB) FET becomes one of the promising structures and has better scalability. However, the on-current of SB FETs is limited by the Schottky barrier at source side. The Modified-Schottky-Barrier (MSB) FETs have been proposed to improve the SB FETs performance. Therefore, the effects of the parameters of the MSB region on device performance and series resistance optimization were simulated by TCAD tools. According to the simulation results, the MSB FETs can be classified into two groups. One is conventional-like devices, and the other one is SB-like devices. For the conventional-likes devices, the high doping concentration and thick thickness of the MSB region would thinner the Schottky barrier thickness at the source side and increase the tunneling current. Therefore, the total conductance is dominated by the gate field induced channel potential barrier lowering. In contrast, for the SB-like devices, the MSB region with lower doping concentration and thin thickness is easily depleted by gate bias. Therefore, the Schottky barrier resistance dominates the total conductance. However, as the device scaling down, the thick MSB thickness would degrade the device performance due to the reduction of effective channel length. Thus, the MSB region with thinner thickness and high doping concentration is needed. On the other hand, the drain-induced-barrier-lowering (DIBL) has to be considered for short channel device. According to the simulation results, the DIBL increases as the MSB doping concentration increases. The optimized conditions for tri-gate MSB FETs with channel length = 32 nm are the MSB thickness = 3 nm and the MSB doping concentration = 3 ×1019 cm-3. The contact resistance is the major part in total resistance. The MSB FETs utilize the high doping concentration at the silicon and silcide interface to reduce the contact resistance. Various silicide thickness structures were used to increase the contact area and reduce the contact resistance. For the conventional-like devices, the optimized silicide thickness is about half of the silicon thickness. For the SB-like devices, the optimized value is about 10 nm due to the tunneling current is concentrated at the Si surface; therefore, the increase of silicide thickenss would not provide additional tunneling current. For tri-gate MSB FETs, the optimized value of planar contact is about 30~35 nm (nearly fully-silicided structure) due to the sidewall channel effect. The optimized value of wrapped contact is quarter of the fin width. However, the on-current and subthreshold swing shows the same silicide thickness dependence. The tradeoff between on-current and subthreshold swing has to be considered. The external loading method was used to extract the series resistance of simulated and real devices. For the conventional-like device, this extraction method is suitable. But for the SB-like devices, this method can not be applied. The extracted series resistance from simulation devices is 160.01 Ω-μm and the specific contact resistivity is lower than 5.5 ×10-8 Ω-cm2 (meet the requirement of ITRS roadmap). The extracted series resistance from contact resistance test structures is about 1~3 kΩ-μm and the specific contact resistivity is 6 ×10-7 Ω-cm2. The contact resistivity of real devices is one order higher than that of the simulatresulted device. The reason may be that the MSB doping concentration is not high enough as expected. The real devices still exhibits a very conventional-like property due to the thicker thickness. It is estimated to be about 10nm. The MSB region of the real devices can be conjectured by the comparison of simulation results and then to improve the process condition to optimize the device performance.