應用數位錯誤截取之混合式三角積分調變器

Abstract

三角積分類比數位轉換器傳統地被使用在低訊號頻帶和高解析度的儀器、聲音和音頻訊號的應用上。在最近幾年，已經有著成長趨勢在發展類比數位轉換器向系統的前端。由於超大型積體電路技術在尺寸上的縮減，高效能的數位系統能被實現。類比數位轉換器必須在類比和數位資料的介面提供更高的動態範圍。因此，能完成用在寬輸入頻帶的無線和有線通訊系統上的高解析度三角積分類比數位轉換器變成愈來愈重要。

在這論文裡，連續時間調變器的設計流程將被呈現，並且一個應用於藍芽技術之100MHz取樣頻率和1MHz訊號頻帶的運算放大器連續時間三角積分類比數位轉換器被實現。此設計被製造於台積電0.18微米互補式金氧半導體製程。量測的訊號失真雜訊比為56.8dB而動態輸入範圍為60dB。功率消耗在1.8V電源供給下為22.2毫瓦。

另一個三角積分設計是去結合連續和離散時間調變器的優點。它是應用數位錯誤截取之混合式三角積分調變器。此設計製造於台積電0.13微米互補式金氧半導體製程。模擬結果在62.5MHz取樣頻率和2MHz訊號頻帶下，訊號失真雜訊比為60.6dB。這樣規格的調變器可以應用在無線通訊系統WCDMA上。功率消耗在1.2V電源供給下為12.17毫瓦。

Sigma-delta analog-to-digital converters (ADCs) are traditionally used in instrumentation, voice, and audio applications that require low signal bandwidth and high resolution. In recent years, there has been a growing trend to move ADC towards the system front-end. Due to the scaling in VLSI technology, high performance digital systems can be realized. The ADC has to provide a higher dynamic range for the interface between analog and digital data. Therefore, sigma-delta ADCs which can achieve high resolution with wide input bandwidth for wireless and wireline communication systems becomes more and more important.

In this thesis, the design flow of the continuous-time (CT) modulator is presented and a 100MHz CT single-bit active-RC sigma-delta modulator with 1MHz signal bandwidth for Bluetooth application is implemented. The design has been fabricated by TSMC 0.18μm CMOS process. The measured SNDR is 56.8dB and the dynamic range is about 60dB. The power consumption is about 22.2mW at 1.8V supply.

The other sigma-delta design is to combine the advantages of the CT and discrete-time (DT) modulators. It is a hybrid sigma-delta modulator with digital error truncation. The work is designed in TSMC 0.13μm CMOS process. The simulation result shows 60.6dB SNDR for 62.5MHz sampling frequency and 2MHz signal bandwidth. With such specification, the modulator can be applied to WCDMA wireless communication system. The power consumption is about 12.17mW at 1.2V supply.