操作在1.8伏特低突波每秒取樣5億次之10位元數位類比轉換器

Abstract

隨著IC設計及製造技術的演進，向來扮演訊號處理重要角色且對電路設計考量要求甚高的DAC電路如今也在SOC的趨勢下常被整合到系統晶片內。DAC應用在各種無線通訊的規格上，當通訊應用上的頻寬增加時，所需的Nyquist DAC的轉換率也相對要求越高，本論文將轉換率訂在500MS/s，達到802.11n的規格要求。並且在可攜式電子產品上，我們需要低功率的電路設計。 目前發表的Nyquist DAC文獻中，current steering DAC是最被廣泛使用的，因為它本身不需要做輸出級放大器電流╱電壓轉換，且電路內部不需要用到電容來做節點的充放電。設計上可達到高速高解析度的效能。在通訊系統的應用中，頻域上的表現(SFDR、SNR)通常要比靜態規格(DNL、INL)來的重要許多，所以特別探討在開關信號對輸出電流所造成的突波影響，造成monotonicity變差，而這也是一般current steering DAC會比電阻式或電容式DAC要來的差的部份。在此提出Multi-finger的技術來降低突波大小，優點是不需額外的電路造成功率消耗與面積的增加。論文後面設計一個4bits binary＋6bits thermometer的segmented架構且操作在500MS/s的10bits DAC來驗證降低突波的效果，此數位類比轉換器採用TSMC 0.18um 1P6M mixed-signal CMOS製程來實現，核心晶片面積是0.175mm2，加上PAD之後為0.65mm2。

In the recently years, wireless communication systems require high speed and high resolution digital-to-analog converters. Current-steering DAC is a particularly appropriate architecture for these applications. These DAC’s specification in dynamic performance, are more important than static performances including INL and DNL in wireless communication systems. DAC’s dynamic performances are limited by output impedance and low output swing in the low voltage design, besides, glitch energy also manly degrades the SFDR. In this thesis, a 1.8V 10-bit 500MHz, low glitch energy current-steering digital-to-analog converter (DAC) is presented. This DAC is segmented into 4 LSBs binary-weighted and 6 MSBs unary cells. A “multi-finger” technique is used to reduce the worst case of glitch energy. The post-layout simulation in the 500MS/s results the glitch energy is only 0.4 pVs. The SFDR achieve 74 dB with a full-scale 49 MHz input frequency. The integral nonlinearity (INL) and differential nonlinearity (DNL) are less than 0.07 LSB and 0.06 LSB. The power consumption is just only 14mW at maximum sampling rate.