DBR模式在記憶體晶圓針測廠之應用

Abstract

晶圓針測 (Wafer Probing) 為半導體晶圓製造完成後驗證產品良率之重要製程。由於半導體之景氣循環波動程度加劇，現有的半導體整合元件製造廠為專注於核心競爭之發展，多選擇將後段之測試與封裝製程外包，使得專業測試廠之規模日漸加大。半導體測試設備本身具有高產品針對性及高投資金額等特性，隨著產品及製程之快速發展，測試設備之單價亦不斷提高，使得專業半導體測試廠之資本支出不斷的向上攀升。同時，測試成本佔單一IC之總成本比例亦隨著產品的積集度與複雜度不斷攀升，故測試業者又往往面對每年客戶測試單價調降之要求。由於晶圓針測製程位於整個晶圓生產製造之最末端，故客戶對測試之生產週期時間 (cycle time) 之要求相當嚴格。加上前段晶圓廠來料之不確定性，使得晶片測試業者常面臨滿足客戶生產週期時間的要求與提升設備有效利用率(Overall Equipment Efficiency, O.E.E)的兩難困境□。目前大多數的有關晶圓針測廠的排程之研究多數集中於數理模式之推導或以系統模擬方式進行排程系統設計。唯這些數理模式之推導過程中或系統模擬通常會做許多的假設與限制，然而在實務的生產應用上，這些假設與限制經常會面臨實務環境的挑戰。本論文之研究在於利用限制理論中之限制驅導式排程 (DBR, Drum – Buffer – Rope)，針對實務生產環境，對晶圓針廠測廠的生產排程提供一套簡易直觀的生產管理模式，俾兼顧生產週期時間 (cycle time) 與設備有效利用率，以供做晶圓針測廠之生產排程作業參考。

Wafer probing is the critical process to justify the wafer yield after wafer fabrication. In the semiconductor industry, it is inconceivable to other business in the near several years that business conditions changes fast and with violent competition. The IDM ( Integrated Device Manufacturer ) now only focus on their core competence, they chose to outsource the backend process to third party so the professional testing foundry becoming more and more scalable. The testing equipment is highly device selected and heavy capital investment machine. With the progress on product and process, the capital investment on testing equipment is getting higher and higher. At same moment, the proportion of testing cost on overall IC cost is still increasing, so the customer demands testing hourly rate reduction strongly. Besides, because the wafer probing process is last process of wafer fabrication, the customers demand very much on production cycle time. Unfortunately, the testing house always faces on the uncertainty of wafer shipment from FAB, so how to take consideration and cycle time and equipment efficiency both has become the challenging issue for testing house now. Most of researches on scheduling for wafer probing process focus on mathematical or simulation model. But the user they need setup some assumptions and constraints to use those models, but some of those assumptions are not so practical in real world. This essay is to build up one straight forward way to handle production scheduling model for memory wafer testing house with DBR (Drum-Buffer-Rope) method of TOC (Theory of Constraint) to take consideration of cycle time and test equipment efficiency both.