運用GasP之低功耗一對多對一結構

Abstract

現今電路設計的趨勢朝向低耗電發展，但也常常會因此而喪失其原本電路的效能，所以擁有低功耗和高效能的電路更具優勢。在本篇論文中，我們提出一個低功耗且高效能一對多對一結構先進先出裝置之設計與實作。它是基於GasP的電路模組所延伸出來的系統，且為了實作此系統，我們提出一個方法可以將此系統的演算法轉換成相對應之GasP的電路模組。接著為了評估先前提出的系統演算法優劣，我們在實作電路前會概略評估此演算法對應出來的電路模組是否符合低功耗和高效能的實作目標。最後我們分別實作了多個先進先出裝置來做比較，其中它們分別為十級和十八級且皆為一個位元儲存空間，於每秒三十億筆資料下以TSMC 180奈米製程模擬。結果指出一對多對一結構先進先出裝置在耗電方面幾乎擁有最好的表現，特別在十八級時可以達到多一倍的節能結果，且在更多級數的先進先出裝置更可顯現出其優勢。

The current trend of circuit design is towards low power, but the performance is often degraded. Therefore the circuits with power-efficiency and high performance are superior. This thesis presents a low power and high performance 1-n-1 structure FIFO implementation, based on GasP modules. In order to implement the system, we explain a method to transform the algorithm of systems into the corresponding GasP modules. Then we derived several equations to analysis the algorithm to conform our purpose before we really implement our design. Finally, we compared the proposed structure with other structures. The depths we compared are ten and eighteen, and the width is one bit. We assume that the environment sends three billion data items per second to the FIFOs and it is simulated with the TSMC 180nm process. The result indicates the 1-n-1 FIFOs almost have the best outcome. In particular, the 1-n-1 FIFO with eighteen stages has one time improvement more than the square FIFO, and the predominance is more obvious when the depth of FIFOs becomes larger.