奈米尺寸金氧半場效電晶體之重要製程開發

Abstract

半導體工業自1970 年代以來，成功地把電晶體的尺寸與製造成本，隨著時間以指數的方式減小。同時，電晶體的效能在過去的幾十年間也持續地增強，並且在可預見的未來也被預期必須能繼續提升。現代的超大規模積體電路(VLSI)極度仰賴應力工程，氧化層厚度微縮，極淺接面，以及通道結構之設計，以期提升電晶體效能並且維持合理的短通道電晶體靜電特性。我們在本論文中，針對以上所提及的重要製程模組進行討論，並且提出利於製程整合又符合成本效益的改善方案。

首先，我們以載子遷移率之一致性(mobility universality)為基礎，提出了一個新穎的方法用以萃取源極/汲極串聯電阻(Rsd)。本方法的優點源自於使用特定的偏壓條件所創造的高電場之下，固定的載子遷移率。這個的特性的應用，是第一次在文獻中被討論。源極/汲極串聯電阻可以使用單一電晶體元件的直流電流-電壓量測所萃取，而不需要知道閘極氧化層厚度，閘極長度，有效通道寬度。正是這一個特點，使得本方法特別適用於短通道電晶體。本方法被廣泛的實驗資料所驗證，隨後被用在評估本文所提出各個製程。

由毫秒退火(millisecond-annealing， MSA)所促成的全矽化閘極(FUSI-gate)技術，首次由本論文提出。這個特殊的技術使用毫秒退火於鎳矽化物(nickel silicide)相變化製程，導致具有強伸張力的全矽化閘極，進而施加壓縮力於通道區域。對於欲防止產生全矽化閘極的區域，氮原子的離子植入提供了良好的選擇性。前人所提出的全矽化閘極製程，普遍需要化學機械研磨製程(CMP)，複晶矽凹陷製程，以及額外的微影光罩顯影製程。相較之下，本方法的製程整合架構十分符合成本效益。增強的電洞遷移率與被消除的複晶矽空乏效應(polysilicondepletion effect)，共同導致p-型電晶體推動電流的顯著提升。本技術亦實現了均勻的全矽化閘極形成，直下到30 奈米的閘極長度。

對於調變嵌入式矽锗(e-SiGe)之尖端與通道區域的距離(proximity)，我們提出一個新穎的作法。以傳統的技術而言，繁複的蝕刻製程搭配隔離物(spacer)結構是常見的方法。然而，由製程所引發的嵌入式矽锗之proximity 偏差卻又導致嚴重的p-型電晶體之效能偏差。在本文中，我們使用在氫氣環境中的熱處理，達到了極度接近又能自行對準的嵌入式矽锗之proximity。相異於傳統的作法通常使用隔離物去定義嵌入式矽锗之proximity，我們所提出的技術可以將嵌入式矽锗之尖端自動對齊至閘極的邊緣。本文的論點獲得了穿透式電子顯微鏡分析之證實。P-型電晶體效能也獲得顯著的提升。

提高閘極電壓的overdrive headroom (Vg-Vth) 對於低供應電壓之奈米尺寸電晶體非常的關鍵。除了在傳統上常使用的次臨界電流斜率(sub-threshold swing)以外，我們提出了一個新的指標，“Vth_lin-Vth_gm”，用以描述電晶體開-關轉變的急劇程度。這個新指標在低供應電壓及低臨界電壓之操作環境之下，益顯得重要，因為它佔據了閘極電壓在turn-on 之前愈來愈大的部份。藉由使用一個新穎的極淺接面離子植入技術，我們增強了電晶體效能並且降低了電晶體受到供應電壓不穩定所影響的敏感度。這應歸功於快速的開-關轉變與載子遷移率的增加。

The semiconductor VLSI technology is so successful that the transistor feature size and cost have been reduced exponentially with time since 1970s. Meanwhile, the transistor performance has increased constantly in the past decades and is expected to improve in the foreseeable future. The modern VLSI technology deeply relies on mechanical strain engineering, equivalent-oxide-thickness (EOT) reduction, ultra-shallow-junction (USJ) formation, and channel structure design for the purpose of boosting transistor performance and maintaining reasonable electrostatic characteristics of the short-channel transistors. In this dissertation we discussed and proposed novel methods to improve the aforementioned key process modules in an integration-friendly and cost-effective manner.

At first, a novel source/drain parasitic series resistance (Rsd) extraction method was proposed on the basis of carrier mobility universality. The merit of the method stems from the specifically arranged bias conditions in which the channel carrier mobility remains constant for high vertical electric fields. Rsd can be extracted using simple DC I-V measurements on a single test transistor without requiring information such as gate-oxide thickness, physical gate length, or effective channel length. It is this unique property which makes this method suitable for short-channel transistors. This method was verified with extensive experimental data and then utilized to evaluate the efficacy of the propose processes in the following chapters.

A novel millisecond-annealing-assisted fully-silicide (MSA-assisted FUSI) gate formation was discussed for the first time. This unique technique utilized an MSA for nickel silicide phase transformation, leading to a highly tensile FUSI gate electrode that exerts compressive stress in the channel region. Great selectivity of FUSI-gate formation was realized by implanting nitrogen in the area where FUSI-gate was to be prevented. The proposed integration scheme is highly cost-effective as compared with the conventional FUSI-gate process, which may need chemical-mechanical-polish (CMP), polysilicon recess, and extra lithography mask layers. Significant improvement in p-type transistor driving current was thereby achieved resulting from enhanced hole mobility and the elimination of polysilicon depletion effect. Uniform FUSI-gate formation across various transistor dimensions was achieved with gate electrode feature size down to 30nm.

A novel process was proposed to modulate the distance, or proximity, between the tip of embedded silicon-germanium (e-SiGe) and the channel region in pMOSFETs. Traditionally, sophisticated etching treatment was adopted in a spacer structure; however, process-induced variation in the e-SiGe proximity may lead to serious variation in pMOSFET performance. In this dissertation, an extremely close proximity was achieved using self-aligned silicon-reflow (SASR) in hydrogen ambient. As opposed to the conventional approaches which had e-SiGe proximity determined by spacer width, the tip of e-SiGe with SASR can be positioned flush with the gate edge as corroborated by transmission-electron-microscopy (TEM) analysis. Significant improvement in pMOSFET performance was also measured.

Enlarging gate voltage overdrive headroom is crucial to low-Vdd operation for nano-scale MOSFETs. We defined a new index, “Vth_lin-Vth_gm“, in order to describe the on-off transition abruptness in addition to the conventionally used index, sub-threshold swing. This new index is increasingly important to the advanced nano-scale MOSFETs for low-Vdd and low-Vth operation because it comprises an increasing portion of gate voltage consumed before turn-on. By introducing a novel USJ ion implantation (I/I) technique with reduced halo I/I dose, enhanced transistor performance and low Vdd-sensitivity were achieved because of quick on-off transition and improved carrier mobility.