適用於高能源效率晶片之可感知變異超低電壓設計

Abstract

本論文提出一具備高能源效率設計之動態電壓頻率調整平台。高能源效率設計包括超低電壓溫度感測器、可感知變異之頻率產生器、高可靠度之超低電壓靜態記憶體與先進先出記憶體。以上述先進先出記憶體作為驗證電路，實現一個高穩定性的動態電壓頻率系統設計。 超低電壓全晶上頻率基底之溫度感測器可工作於0.4V與0˚C~100˚C溫度範圍內，每秒可有效偵測45k次，使用一位元校正機制下，僅有-1.81˚C~+1.52˚C的溫度誤差，其實現於TSMC 65nm製程下，使用面積為990μm2。Logical effort是數位設計者常用之技巧，但傳統的Logical effort並未考慮CMOS操作於不同工作區間，以及溫度和製程對其造成的影響，本論文提出一個可應用在0.1V~1V間的統一Logical effort，並且可減少溫度和製程變化所造成的延遲估計誤差。根據上述的統一Logical effort，本論文設計一超低電壓頻率產生器，其內建的感測器可提供資訊動態自我調整鎖定區間誤差，此技術實現於UMC 65nm製程下，可產生625kHz及5MHz最高頻率輸出分別在0.2V與0.5V下，且其消耗的功率僅各有0.18μW與5.17μW，同時本頻率產生器可合成出1/8至4倍於參考頻率之輸出。 本論文設計一運用打斷正回授正反器迴圈以改善寫入能力之9T靜態記憶體，本記憶體同時具備讀取緩衝以增進寫入可靠度與降低漏電電流，位元交錯結構也可與本靜態記憶體交錯運用以提高軟錯誤的抵抗能力，本靜態記憶體實現於UMC 65nm製程下，可工作於電壓為0.3V以909kHz頻率操作且僅消耗最低能源3.51μW。為提供無線近身網路系統良好的儲存單元，本論文設計一以10T靜態記憶體基底之先進先出記憶體，該先進先出記憶體實現於UMC 90nm製程下，可工作於電壓為0.4V以50kHz頻率操作寫入僅消耗最低能源2.09μW，同時以625kHz頻率操作讀取僅消耗最低能源2.25μW。 本論文提供一具備高能源效率設計之動態電壓頻率調整平台，以8T靜態記憶體基底之先進先出記憶體作為展示電路，提供兩種工作模式：低電壓(0.3V)與高效能(0.5V)，若其持續工作於低電壓模式時可節省69.5%功率消耗，本平台可適用於高穩定性之無線近身網路應用。

Energy efficient design is a key focus in emerging energy-constrained platforms. Dynamic voltage frequency scaling (DVFS) platform with energy-efficient designs are presented in this thesis. Ultra-low voltage temperature sensor and variation-aware clock generator are implemented to enable DVFS platform. Robust near-/sub-threshold SRAM/FIFO memories are designed as the test vehicle of DVFS platform. An ultra-low voltage fully integrated frequency-domain smart temperature sensor is presented. With one-point calibration, a -1.81˚C~ +1.52˚C inaccuracy over a 0˚C~100˚C temperature operation range has been measured for 12 test chips. At a conversion rate of 45k samples/s, the proposed temperature sensor consumes an average power of 520nW and achieves 0.49˚C/LSB at 11-bit output resolution. It occupies only 990μm2 in a TSMC 65-nm general purpose bulk CMOS process. The voltage-/temperature-induced delay estimation error of conventional logical effort is much more severe in near-/sub-threshold region. Super-/near-/sub-threshold logical effort models are presented to eliminate delay estimation error caused by voltage and temperature variations. A near-/sub-threshold programmable clock generator is also presented in this thesis. The major challenge of the ultra-low voltage (ULV) circuits is that the lock-in range of the delay line is easily affected by the environmental variations. In the proposed clock generator, there is a PVT compensation unit which consists of a set of delay line and a PVT detector. The unit is responsible for adjusting the lock-in range of clock generator to guarantee successful clock lock. In addition, it has the ability to generate the output clock with frequency from 1/8 to 4 times of the reference clock. The clock generator has been designed using UMC 65nm CMOS technology. The frequencies of reference clock are 625 KHz at 0.2V and 5MHz at 0.5V. The power consumptions are 0.18μW and 5.17μW, respectively, at 0.2V and 0.5V. The core area of this clock generator is 0.01mm2. A 9T SRAM bit-cell is presented to enhance write ability by cutting off the positive feedback loop of SRAM cross-coupled inverter pair. In read mode, an access buffer is designed to isolate storage node from read path for better read robustness and leakage reduction. Bit-interleaving scheme is allowed by incorporating the proposed 9T SRAM bit-cell with additional write-wordlines (WWL/WWLb) for soft error tolerance. A 1Kbit 9T 4-to-1 bit-interleaved SRAM is implemented in 65nm bulk CMOS technology. The experimental results demonstrate that the test chip minimum energy point occurs at 0.3V supply voltage. It can achieve an operation frequency of 909kHz with 3.51μW active power consumption. An ultra-low power (ULP) 16Kbit SRAM-based first-in first-out (FIFO) memory is also presented for wireless body area networks (WBANs). The proposed FIFO memory is capable of operating in ultra-low voltage (ULV) regime with high variation immunity. An ULP near-/sub-threshold 10 transistors (10T) SRAM bit-cell is proposed to be the storage element for improving write variation in ULV regime and eliminate the data-dependent bit-line leakage. The proposed SRAM-based FIFO memory also features adaptive power control circuit, counter-based pointers, and a smart replica read/write control unit. The proposed FIFO is implemented to achieve a minimum operating voltage of 400mV in UMC 90nm CMOS technology. The write power is 2.09μW at 50kHz and the read power is 2.25μW at 625kHz. Finally, a 512-word by 16-bit (8kb) subthreshold asynchronous first-in first-out (FIFO) memory is presented for wireless body area networks (WBANs). Meanwhile, A 1kb dynamic voltage scaling 8T SRAM-based FIFO memory is implemented to operate between 0.5V (near-threshold) and 0.3V (subthreshold) in UMC 65nm technology with 0.535μW at 625kHz and 0.163μW at 20kHz power consumption, respectively. The proposed DVS FIFO memory can provide up to 69.5% power savings when low-power mode is always engaged, and there is no power overhead if the period of low-power mode is longer than 48.66μs. It is suitable for healthcare applications equipped with DVFS capability.