低電壓操作靜態隨機存取記憶體的設計與實現

Abstract

靜態隨機存取記憶體在系統晶片中扮演著很重要的角色，由於製成與元件變異惡化，傳統6T靜態隨機存取記憶體的穩定性遇到很嚴峻的挑戰。在此論文，提出非對稱性虛接地寫入輔助偏壓技術，與正回受感測維持器來克服單端靜態隨機存取記憶體的寫入限制，透過此技術，寫入安全限度獲得兩倍的改善，寫入速度也提昇超過10倍。 此外,在此論文提出一種新式的8+1T 靜態隨機存取記憶元件，其寫入資料控制式寫入操作，與串連存取閘架構，可減少功率的消耗，並提昇低壓操作的可靠度，還有其串疊式讀取埠可減少非理想的漏電以增加其讀取的感測範圍。這個新式的記憶元件可改善1.28倍的讀取靜態雜訊邊界，且消除半選元件的干擾，並節省超過10倍的動態寫入功耗。經過模擬,測試晶片在600mV供應電壓、6MHz操作速度下，可達到僅消耗些許μW平均功率消耗。

Static Random Access Memory (SRAM) plays an important role in the System on Chip (SOC) design. The traditional 6T SRAM cell encounters a severe challenge on reliability issue due to the worse process and device variation. In the thesis, an asymmetrical Write-assist virtual ground biasing technique and positive feedback sensing keeper are proposed to overcome the Write restrictions of single-ended SRAM cell. The technique improves ×2 Write margin and over one order of Write time. In addition, a new 8+1T SRAM cell proposed in the thesis. The Data Controlled Write operation and series connected pass-gates structure make the Write operation lower power consumption and higher reliability in low supply voltage operation. The stacked Read-out port also improves the Read-out sensing margin of single bit line. The new cell improves ×1.28 Read static noise margin and saves over one order of active Write power without Write half selected disturbance. The test chip achieves a few μW average power at 6MHz and 600mV supply voltage.