以脈波閂鎖器之存活記憶體單元為基礎之低功率維特比解碼器

Abstract

近來由於無線及可攜式裝置的普及，高速低功率的維特比解碼器成為設計上重要的考量。為了有效降低維特比解碼器的功率消耗，本論文提出一個脈波閂鎖器來實現解碼器的記憶體部分。由於電壓低擺伏的優點及通行電晶體的特性，可降低單一記憶體單元的功率消耗，進而降低資料存取時的功率消耗。模擬結果顯示，在雜訊比為3分貝的環境下，本研究所提出的方法可省下21％的解碼器功率消耗與29％的存活記憶體單元功率消耗。

Recently, a high-speed and low-power Viterbi decoder is needed due to wireless and portable devices. In order to reduce the power consumption of Viterbi decoder, we proposed a full-custom pulse latch as the data storage unit in the survivor memory. Because of the low-swing and the characteristic of pass transistor, the power consumption of single register is reduced, so the power of data access in survivor memory also be reduced. According to the implementation result, 29% of survivor memory power and 21% of overall decoder power could be reduced as Eb/No is 3dB.