CMOS光通信接收機設計

Abstract

近年來隨著多媒體資訊的快速發展，大眾對於資料傳輸效率要求越來越高，像是未來HDMI、USB 4.0等應用的操作速度都希望能超過10 Gbps。但在如此高的操作速度下，傳統銅線傳輸的損耗率和電磁干擾(EMI)等問題已非常嚴重，因此具有低串音(Cross Talk)以及低電磁干擾(EMI)的光纖傳輸特性被視為適合應用於此類高密度高速率的資料傳輸媒介。因此，在互補式金屬氧化物半導體(CMOS)製程下實現小面積、低成本的光纖收發機電路，以期應用於高密度傳輸平台之系統單晶片設計，因此完成一個高整合度的高速光電積體電路(Optoelectronic integrated circuit, OEIC)將是此篇論文的目標。 本篇論文設計了兩顆晶片，分別為相容於90奈米互補式金屬氧化物半導體(CMOS)製程來實現操作於10 Gbps的光電積體電路(Optoelectronic integrated circuit, OEIC)，以及用65奈米互補式金屬氧化物半導體(CMOS)製程來實現操作於40 Gbps的光纖接收端前級電路，希望可以分別將光訊號以及光電流訊號完整地轉換成後端數位可解調之電壓訊號準位。 第一個晶片於90奈米CMOS製程下整合了一個逆偏壓為1.2 V的CMOS積體化光感測器(Photodetector，PD)，一個轉阻放大器(Transimpedance Amplifier，TIA)，一個適應性等化器(Adaptive Equalizer，EQ)，以及一個後級限幅放大器(Limiting Amplifier，LA)於單晶片設計。OEIC提供92 dBΩ的整體增益，並且針對CMOS PD的物理特性利用適應性的類比等化器(Equalizer)進而讓OEIC可以操作到10 Gbps的資料速度，而OEIC的輸入功率靈敏度為-4 dBm。在整顆晶片耗功130毫瓦。晶片面積是0.57 mm2¬。 第二個晶片為一個操作於40 Gbps的光通訊接收機，整體架構中包含了一個轉阻放大器(Transimpedance amplifier , TIA)和一個後級限幅放大器(Limiting Amplifier , LA)，架構中運用了分離節點式串聯峰化、並聯峰化的高頻補償技術、以及逐級套疊式主動回授(Nested active feedback)架構等方法來提升接收機整體效能，進而提供92 dBΩ的整體轉換增益、35 GHz的-3dB頻寬、以及800 mVpp的差動輸出擺幅，平均的輸入參考雜訊(Input-referred noise) 為14 pA/√Hz。此晶片採用65 nm CMOS標準製程，晶片面積為0.825 mm2¬。

With the rapid development of multimedia information, people need higher data transfer efficiency. Many applications such as HDMI cable and USB 4.0 are expected to design more than 10 Gbps operating speed. Data communication over optical links benefits from wider bandwidth and lower channel loss compared to electrical counterparts. Fiber channels are widely deployed for long haul telecommunications as network backbone. Optical links are drawing more and more attentions in these applications for their superiorities in less cross-talk, lower EMI, and fewer equalizer needed for data rate up to 10 Gbps. As a result, implementation of optoelectronic integrated circuits (OEIC) in CMOS technology with small form factor and low cost becomes a challenging and practical research topic for the SOC design of the high density communication platform. This thesis consists of two chips, respectively, 10 Gbps CMOS OEIC with adaptive equalizer in 90-nm CMOS technology and 40 Gbps optical receiver analog front-end in 65 -nm CMOS technology. The 10 Gbps CMOS OEIC consists of a novel spatially-modulated photo detector (SMPD) under a low reverse-biased voltage of 1.2 V, a low-noise trans-impedance amplifier (TIA), a post limiting amplifier, and a adaptive equalizer on a single chip. The optical receiver is capable of delivering 92 dBΩ conversion gain when driving 50 Ω output loads. The input sensitivity of the optical receiver is about 30 □App, and the measured responsivity of the photo detector is about 37 mA/W. The input sensitivity of the optical receiver is -4 dBm for BER less than 10-12 under 27 - 1 PRBS test pattern. The core circuit dissipates 130 mW. Fabricated in 90 nm CMOS technology, chip size is 0.57mm2. The 40 Gbps optical receiver analog front-end integrating both transimpedance amplifier and limiting amplifier is presented. Incorporating nested feedback, split-node series peaking, and shunt peaking techniques, the optical receiver provides a conversion gain of 92 dBΩ, -3dB bandwidth of 35 GHz, and 800mV differential output voltage swing. The average input referred noise of the optical receiver is 14 pA/√Hz. The core circuit dissipates 168 mW. Fabricated in 65 nm CMOS technology, chip size is 0.825mm2.