完整後設資料紀錄
DC 欄位語言
dc.contributor.author余介恩en_US
dc.contributor.author林進燈en_US
dc.contributor.author周志成en_US
dc.date.accessioned2014-12-12T01:27:48Z-
dc.date.available2014-12-12T01:27:48Z-
dc.date.issued2008en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT079612596en_US
dc.identifier.urihttp://hdl.handle.net/11536/41914-
dc.description.abstract在人體所有的生理訊號中,其訊號振幅皆非常微弱,亦容易被受測者本身、量測環境及設備等因素所影響,故本論文提出適用於各種電生理訊號擷取之晶片設計。除了一般著重的低功率、低雜訊之外,同時提高共模訊號拒斥比(CMRR)與電源漣波拒斥比(PSRR),並將整體多通道前端電路整合實現在單一晶片上,不需要任何外接元件,除了兼具成本與晶片面積效益,亦可降低因複雜的接線對生理訊號在量測時所造成的干擾,使後端處理及分析的訊號品質能夠更為精確。另外,在系統加入了數位控制介面,根據不同生理訊號的需求,利用數位訊號去控制選擇所要的訊號放大倍率與系統頻寬。 本論文所設計的生理訊號擷取晶片包含:截波穩定式儀表放大器(CHS-IA)、類比多工器、切換式電容低通濾波器(SC-LPF)、非重疊時脈產生器(Non-Overlapping Clock Generator) 、切換電容式可變增益訊號放大器(SC-VGA)及多級雜訊移頻三角積分類比/數位轉換器(MASH 2-1-1 tri-level ΣΔ ADC)等電路。整個電路設計使用TSMC 0.18μm CMOS 1P6M 製程技術來實現,而整體晶片面積為1.9198 × 1.9198 。由模擬結果顯示,在頻率1024Hz下,可獲得訊雜比90 dB,16位元解析度的效能。在操作電壓1.8V下,總消耗功率約998μA。zh_TW
dc.description.abstractDue to properties of low-amplitude and non-stationary, most of biomedical signals are easily influenced by examined persons, measured environment, and electronic devices. A novel analog circuit design is proposed in this thesis, which is suitable for various biomedical signal acquisitions. In addition to the consideration of low power and low noise, the multi-channel mixed-signal front-end integrated circuit (MSFEIC) is designed. This circuit is realized into a single chip without any external component. It can not only reduce the number of outer components, but also enhance a better signal-to-noise ratio enormously. In addition, to select system gain and bandwidth corresponding to different amplitude and frequency of biomedical signals, the controllable digital interface is also designed and integrated into MSFEIC. In this thesis, MSFEIC design is composed of four chopper-stabilized instrumentation amplifiers (CHS-IA), a switched-capacitor variable gain amplifier (SC-VGA), a switched-capacitor low-pass filter (SC-LPF), a non-overlapping clock generator, and a cascaded 2-1-1 tri-level sigma-delta analog-to-digital converter (MASH 2-1-1 tri-level ΣΔ ADC). These circuits have been integrated into a single chip of the total area of 1.9198×1.9198mm2 by using TSMC 0.18μm CMOS Mixed-Signal RF General purpose MiM Al 1P6M 1.8&3.3V process. For the simulation results, the proposed chip can achieve 90 dB of SNR, 16-bit resolution at 1024Hz. The total power consumption is about 998□W under 1.8V supply.en_US
dc.language.isoen_USen_US
dc.subject生理訊號zh_TW
dc.subject腦電圖zh_TW
dc.subject截波穩定式儀表放大器zh_TW
dc.subject切換式電容低通濾波器zh_TW
dc.subject切換電容式可變增益訊號放大器zh_TW
dc.subject多級雜訊移頻三角積分類比/數位轉換器zh_TW
dc.subjectBiomedical signalen_US
dc.subjectchopper-stabilized instrumentation amplifieren_US
dc.subjectswitched-capacitor low-pass filteren_US
dc.subjectswitched-capacitor variable gain amplifieren_US
dc.subjectMASH 2-1-1 tri-level ΣΔ ADCen_US
dc.title混合訊號前端積體電路應用於可攜式生醫訊號擷取系統zh_TW
dc.titleA CMOS Mixed-Signal Front-End IC for Portableen_US
dc.typeThesisen_US
dc.contributor.department電控工程研究所zh_TW
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