The electrical characteristics of the amorphous silicon thin film transistors with dual intrinsic layers

Abstract

The amorphous silicon thin film transistors (a-Si:H TFTs) with dual intrinsic layers, namely, a bottom a-Si:H deposited at a low deposition rate and an upper layer at a high deposition rate, were investigated to improve the manufacturing throughput. It was found that the high deposition rate for the upper layer resulted in high density of states and low mobility and high threshold voltage. Although a-Si:H TFTs with high deposition rates for the upper layer still had an I-on/I-off ratios higher than 10(6) and saturation mobility higher than 0.4 cm(2)/V s, the deposition rates of 1786 and 3340 Angstrom/min exhibited a significant current crowding and led to low mobility and on-current in the linear region. On the other hand, a-Si:H TFTs with deposition rate of 1170 Angstrom/min for the upper layer achieved similar characteristics as those with single layer deposited at deposition rate of 482 Angstrom/min. Furthermore, the stress stability for deposition rate of 1170 Angstrom/min also showed a threshold voltage shift similar to that of a single-layer one. This indicated that the deposition rate of the upper layer for dual-layer a-Si:H TFTs must be properly chosen for applications in high resolution LCDs.