完整后设资料纪录
DC 栏位语言
dc.contributor.author赵自强en_US
dc.contributor.authorTzu-Chiang Chaoen_US
dc.contributor.author黄威en_US
dc.contributor.authorWei Hwangen_US
dc.date.accessioned2014-12-12T01:33:50Z-
dc.date.available2014-12-12T01:33:50Z-
dc.date.issued2005en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT009111567en_US
dc.identifier.urihttp://hdl.handle.net/11536/43312-
dc.description.abstract本论文提出新的频率搜寻演算法以及低功率的架构来设计一个低功率的全数位锁相回路。在演算法方面,使用新的频率搜寻演算法能使我们的全数位锁相回路在18个参考周期内完成相位锁定。而在电路设计方面,使用新的架构来实现我们的电路可以使频率比较器,相位侦测器以及增益产生器整合在一个电路之中。在论文中,我们亦提出一个新的低功率数位控制震荡器而其频率震荡范围为200到750万赫兹。总体而言,我们所提出的全数位锁相回路具有快速锁定,面积小以及低功率消耗的特性。

在量测方面,时脉抖动是锁相回路重要的参数之一,而此参数的量测通常需要额外的量测仪器。使用额外的仪器来量测此参数会造成讯号严重的失真,所以在本论文中,我们使用内建时脉抖动量测技术来量测时脉抖动。

本论文以TSMC 0.13um 1P8M CMOS 技术实现。供给电压为1.2伏,总面积为200um X 100um。模拟结果显示当数位控制震荡器频率为560万赫兹时,全数位锁相回路的相位抖动为161.4ps,而总功率消耗为1.7mW。
zh_TW
dc.description.abstractA new architecture and algorithm for the all digital phase-locked loop (ADPLL) with low power design is presented in this thesis. By using the new search algorithm, it can accomplish phase lock process within 18 input clock cycles. By using the new architecture, we can combine the functions of the frequency comparator, phase detector and gain generator in one hard block. Also, a new digitally controlled oscillator structure for low power is presented in this thesis and its frequency range is from 200 MHz to 750 MHz. This ADPLL has characteristics of fast frequency locking, small hard cost and lower power consumption.

Clock jitter is one of main issues for PLL and conventionally jitter measurement rely on the external equipment. But the external equipment distort the tested clock signal seriously, it is a good choice to measure jitter by Built-In Jitter Self Test technique. In this thesis, Built-In Jitter Self Test technique is used for jitter measurement.

The proposed ADPLL is simulated and implemented by TSMC 0.13um 1P8M CMOS technology. The supply voltage is 1.2v and total area is 200um x 100um. The simulation results show that when the DCO operates at 560MHz, the jitter is 161.4ps and the total power consumption of ADPLL is 1.7mW.
en_US
dc.language.isoen_USen_US
dc.subject全数位锁相回路zh_TW
dc.subject低功率zh_TW
dc.subject频率比较器zh_TW
dc.subject相位侦测器zh_TW
dc.subject数位控制震荡器zh_TW
dc.subject时脉抖动zh_TW
dc.subjectADPLLen_US
dc.subjectlow poweren_US
dc.subjectfrequency comparatoren_US
dc.subjectphase detectoren_US
dc.subjectdigitally controlled oscillatoren_US
dc.subjectjitteren_US
dc.title内建抖动测试之低功率全数位锁相回路zh_TW
dc.titleLow Power All Digital Phase-Locked Loop with Built-In Jitter Self Testen_US
dc.typeThesisen_US
dc.contributor.department电子研究所zh_TW
显示于类别:Thesis