適用於正交分頻多工系統之快速傅立葉處理器設計

Abstract

在本論文當中，我們比較了數種不同的快速傅立葉轉換演算法以及硬體架構。並且分析了不同快速傅立葉轉換演算法的算術計算複雜度，和比較數種快速傅立葉轉換處理器硬體架構在硬體成本、工作頻率、處理單元使用率上的優劣。最終，我們使用平行管線式架構來實現一個符合802.11a/g規範的低延遲高面積效益快速傅立葉轉換處理器。硬體實現上，使用聯電0.18微米製程，核心面積為1045微米*1045微米，工作頻率可達54.46 百萬赫茲。

In this thesis, we compared several kinds of algorithms and hardware architectures. We analyzed the computational load of different algorithms and compared their hardware costs, operation frequency and function unit utilizations. Based on the system requirements of IEEE 802.11a/g OFDM, we proposed a modified radix-8 pipeline based architecture to implement a low latency and area efficiency FFT/IFFT processor. The hardware was implemented using UMC 0.18μm technology with core size 1045μm*1045μm and operation speed 54.46MHz.