光纖通訊類比前端電路設計與製作

Abstract

這篇論文分成兩個部分。 首先，我們將介紹一個差動主動回授轉阻放大器。 轉阻放大器差動直流耦合光二極體電流, 所使用的製程為0.18微米CMOS技術。 轉阻增益為56dBΩ， 在光二極體寄生電容為0.2pF的條件下操作的資料傳輸速度能達到3.125Gbps。 輸入端的參考雜訊電流為1.2μArms。 操作電壓為 3..3(V)伏特， 總功率耗損是79(mW)毫瓦。 晶片尺寸是738乘1522(μm2)微米平方。 第二， 我將討論一個增益為90dBΩ光纖前級接收端電路所使用的製程為0.18微米CMOS技術。 在此設計中我將轉阻放大器度(TIA)與自動增益控制電路(AGC)以及限幅放大器(LA)整合成單一晶片， 當驅動50Ω系統時， 接收器前端電路直接把光電流轉化成一個900 mV(pp)的差動輸出信號。 在輸入信號為231-1假亂數訊號時接收器的最小輸入光功率是-13 dBm被容忍的輸入功率能達到0 dBms所能達到的位元錯誤率小於10-12。 接收者前端提供的頻寬為7.86 GHz兒而增益頻寬乘積為248.5THz超過到目前為止所發表設計。 為了達到展延頻寬的目地我们在接收器電路裡採用了立體對稱式電感。 在1.8(V)伏特的供應電壓操作下， 總功率耗損是199(mW)毫瓦。 小片尺寸是1300乘1566(μm2)微米平方。

This thesis is divided into two part. First, a design of the differential active feedback trans-impedance amplifier is discussed. A trans-impedance amplifier with differential dc-coupled photocurrent sensing was integrated in 0.18μm CMOS technology. It achieves 56dBΩ trans-impedance gain and the operating data rate is up to 3.125Gbps with a 0.2pF photodiode capacitance. The input referred noise current is 1.2μArms. Operating under a 3.3V supply, the total power dissipation is 79mW. Chip size is 738μm×1522μm. Secondly, the 90dBΩ optical receiver analog front-end fabricated in a 0.18 μm CMOS technology is discussed. Integrating trans-impedance amplifier (TIA), automatic gain control circuit, and post limiting amplifier (LA) on a single chip, the receiver front-end converts photo current to a differential output signal of 900 mV (pp) directly when driving 50 Ω output load. The sensitivity of the optical receiver is -13 dBm at a bit-error rate of 10−12 with 231 − 1 pseudo-random bits input, and the tolerated input power is up to 0 dBm. The receiver front-end provides a −3 dB bandwidth of 7.86 GHz and a corresponding GBW of 248.5 THz that exceeds prior arts reported to date. 3-D symmetric transformers are utilized in the AFE design for bandwidth enhancement. Operating under a 1.8V supply, the total power dissipationis 199 mW. Chip size is 1300 μm × 1566 μm.