一個背景式校正之全數位式非整數頻率合成器

Abstract

相位雜訊為評估鎖相迴路功能優劣的一個重要指標，而頻寬的決定也會直接的影響到輸出相位雜訊的表現。在一個類比式的鎖相迴路中，頻寬由充電泵電流值、迴路濾波器電阻電容值、振盪器增益所決定。不幸的是，上述均會受到製程物理環境與元件不匹配誤差，使得與原先之設計值有所不同，無法達最佳雜訊頻寬的效果。然而在一個全數位式鎖相迴路中，頻寬由一些已知的參數以及振盪器增益所決定，其中僅剩振盪器增益會受到製程物理環境與元件不匹配誤差影響的變數。 本論文提出一個具有背景式校正的全數位式非整數頻率合成器。自我追蹤與校正振盪器增益的方法，能免除製程物理環境和元件匹配誤差造成振盪器增益的不理想效應，並能在不影響鎖相迴路系統運作於通訊系統下，加於振盪器輸入端一數位訊號，使迴路濾波器輸出端產生一相應訊號，得知其振盪器增益關係式。使用上述量取振盪器增益資訊，直接的校正振盪器增益，可達到校正振盪器物理增益，與還原最佳雜訊頻寬的效果。 另外，時脈抖動特性亦為鎖相迴路的一個重要效能。以往測試鎖相迴路效能多用外部儀器量測時脈抖動，但隨著鎖相迴路操作頻率之提升，測量儀器成本也大大提高。因此晶片上雜訊自我量測的方法，利用振盪器輸入端的頻率控制碼(FTW)計算抖動雜訊，其量測頻率從原本的輸出頻率降低為參考頻率等級，大大減輕了量測儀器的成本。 本論文中的晶片採用TSMC-40nm CMOS製程技術實現，總面積為1.330 x 1.195mm2。晶片量測結果，輸出頻率為8GHz，RMS jitter在整數及非整數架構下分別為3.4251ps及13.019ps。

Phase noise is an important factor, which is used to estimate the performance of phase locked loop, and the choice of the bandwidth could also affect the phase noise directly. In an analog phase-locked loop, the bandwidth depends on the current of charge pump, the passive components in the loop filter and the gain of voltage control oscillator (VCO). Unfortunately, they would differ from the designed values because of the process, voltage and temperature (PVT) variation. However, in an all-digital phase-locked loop, the bandwidth is composed of some well-known parameters and the gain of digital control oscillator (DCO), but only the gain of DCO is unpredictable because of the PVT variation. An all-digital fractional-N frequency synthesizer with background calibration is presented. The background calibration method of the DCO gain could relieve the PVT variation on the DCO gain without affecting the operation of the communication system at the same time. Adding a digital code at the input of the DCO, so that the output of loop filter would generate an opposite signal,able to be recorded to formulate the estimation of the DCO gain. The background calibration method of the DCO gain could restore the loop bandwidth without changing other loop parameters. Besides, jitter performance is another important factor, which is used to estimate the performance of phase-locked loop. But it is difficult to measure the output clock jitter of the high speed phase-locked loop circuit directly. In addition, using external measuring equipment takes the high cost. For the reasons, the on-chip jitter measurement method, which dumps the frequency tuning word from the input of DCO, could estimate the jitter performance by lower frequency. Since the measured frequency changes from output frequency to reference frequency level, the on-chip jitter measurement methodcould release the cost of equipment. Implemented in TSMC-40nm CMOS technology, the total area included PAD is 1.330 x 1.195mm2. The measured output frequency of proposed ADPLL is 8GHz, where the RMS jitter is 3.4251ps in integer-N architecture and 13.019ps in fractional-N architecture.