矽化鎳之熱穩定性與超淺接面應用的研究

Abstract

在現今微縮驅使下，矽化鎳是最常用在先進製程中的金屬矽化物。在矽化鎳熱穩定性及接面特性之研究方面，本論文提出利用高劑量鍺離子佈值來改善其熱穩定性。我們發現在矽基板上，鍺摻雜可提升結塊及二矽化鎳相轉變溫度各攝氏50~100度。而將其利用在高摻雜之n型或p型矽基板上時，因受其它高摻雜離子影響，改善程度只有攝氏50度左右，但是對於n型或p型多晶矽閘極，卻仍保有攝氏100度的改善能力。此外還發現高劑量鍺離子佈值可以改善矽化鎳與矽的介面平坦度。在熱穩定性研究的基礎下，進一步研究n型或p型二極體特性的改善。我們發現對於漏電流而言，雖然有鎳沿著鍺離子佈植產生的缺陷往下擴散之影響，仍可以看出對週邊漏電流降低以及整體漏電流耐溫增加的改善。 為了減少寄生電容及改善短通道效應，電晶體結構趨向多閘極結構，並可能進一步製作在絕緣層上矽(SOI)的晶片上面。由於先將離子植入矽化鎳，再經過退火後，會使得佈值離子被離析到矽中，可形成超淺接面，本論文遂利用此技術在SOI上製做並研究超淺接面之特性。在現今常用的二氟化硼(BF2+)、磷(P+)、砷(As+)離子佈值入矽化鎳後再經由攝氏500~750度的再退火製程，可以發現其具有良好的熱穩定性及可得到遠低於矽化鎳蕭基特接面的漏電流。在此也針對其週邊二氧化矽介面造成漏電流的捕獲能態密度進行探討，藉由閘極二極體(gated-diode)及電荷捕捉(charge pumping)兩種方法量測捕獲能態密度的大小，分析漏電流機制。針對上述兩種在不同基板上製作的超淺接面，我們製作不同的結構來量測此兩種接面的矽化鎳/矽的接觸阻抗。在矽基板上，經過鍺離子佈值後，矽化鎳對高摻雜p型基板的接觸阻抗可以低到10-8 Ω-cm2的數量級，而在SOI上可量到BF2+佈值的接面有2 × 10-8 Ω-cm2的低接觸電阻率，而P+佈值的接面則有偏高的3 × 10-7的接觸電阻率。 最後我們希望利用掃描探針顯微術之ㄧ的Kelvin-Probe Force Microscopy (KPFM)來量測半導體表面電位差，透過常用的的幾種不同一維載子濃度分布測定方法為基準，來推算表面二維載子濃度分布。雖可成功利用在較深的p-n接面剖面濃度的分析，但是空間解析度不理想，尚待改善。 整體而言，本論文研究了利用鍺離子佈植改善矽化鎳的熱穩定性和利用離子植入矽化鎳再經退火之方法改善蕭基特二極體接面的電特性，以及研究了它們的接觸阻抗大小並期待利用KPFM來量測超淺接面深度。

In the ULSI IC industry, as the gate length is being scaled down to the nanometer level, metal silicides are being used as contact materials to reduce parasitic resistance. Among the different silicide materials, nickel silicide is the most popular. In a study on the thermal stability and junction properties of nickel monosilicide (NiSi), I proposed high-dosage germanium ion implantation (Ge I/I > 5 × 1015 cm-3) before silicide formation to improve the thermal stability. The experimental results showed that Ge implantation resulted in an improvement in both the phase transformation and agglomeration temperatures of NiSi by 50~100 □C. We applied this technique to NiSi contacted n+-p and p+-n shallow junctions. The improvement was reduced to 50 □C due to the high concentration of dopants in the bulk-Si substrate. However, the application to a highly doped poly-Si gate yielded in improvements by 100 □C. Additionally, for samples implanted with Ge I/I before NiSi formation, we found a very smooth NiSi/Si interface at 750 □C. Although fast Ni diffusion via the defects induced by the Ge I/I was present, we still observed smaller peripheral leakage currents and better thermal stability by electrical characterization.

Multi-gate transistors fabricated on silicon-on-insulator (SOI) wafers were developed against the short channel effect and demonstrated lower parasitic capacitance. When using the implant-to-silicide (ITS) technique, the implanted atoms diffused out of the silicide and piled up at the silicide/silicon interface during the post-annealing process. The segregated atoms formed an ultra-shallow junction. In my study, the ITS technique was utilized to fabricate lateral modified Schottky barrier (MSB) junctions on SOI wafers. BF2+, As+, and P+ dopants were used and the electrical characteristics of the diodes after annealing from 500 □C to 750 □C were compared. It was found that the MSB junction maintained a good thermal stability and had much lower leakage currents than the NiSi contacted SB junction. We also measured the interface trap density between the Si and SiO2 of MSB p+-n and n+-p diodes. Charge pumping and gated diode methods were used to measure the interface trap density and analyze the leakage current mechanism for MSB diodes. We designed contacts and structures with different dimensions to measure the contact resistance of the NiSi/Si interface for a p+-n junction with Ge I/I on bulk-Si and MSB junctions on SOI. The specific contact resistivity for the p+-n junction with Ge I/I was around 10-8 Ω-cm2, 2 × 10-8 Ω-cm2 for the p+ MSB contact, and 3 × 10-7 Ω-cm2 for the n+ MSB contact. Finally, we demonstrated a two-dimensional (2-D) carrier/dopant profiling technique that uses Kelvin-probe force microscopy (KPFM) to measure the surface potential of a p-n junction. The correlations between the surface potential difference measured by KPFM and the results of secondary ion mass spectroscopy (SIMS), the surface carrier concentration obtained by spreading resistance profiling, and the capacitance-voltage method were established. These results indicate that 2-D carrier depth profiling of a p-n junction was successfully achieved. To summarize, the thermal stability and junction properties of NiSi were improved by Ge I/I and ITS techniques, respectively. The contact resistances were measured, and a 2-D carrier depth profiling technique was proposed, which is expected to be very useful for NiSi contacted ultra-shallow junction applications in the future.