應用於鎖相迴路之高解析度相位頻率偵測法

Abstract

我們提出一個應用於鎖像迴路之高解析度相位頻率偵測法。在鎖定過程中的頻率搜尋模式和相位維持模式裡，共用單一的相位偵測器輸出，借此得到相位和頻率資訊。當頻率搜尋完成，參考訊號的相位和回授訊號的相位之間存在的相位誤差將趨近於零。因此上述的方法可以降低鎖定迴路的電路複雜度和鎖定時間。 所提出的電路架構被實現在UMC 90nm 1P9M standard CMOS製程，經模擬結果顯示時脈抖動為80ps，功率消耗為2.46mW，輸出頻率為1.25GHz，並且具有八個相位輸出，晶片面積為140um×110um。

We proposed a high resolution phase method of frequency detection for all digital phase locked loop. We use single output of the phase detector to obtain phase and frequency information for both frequency search and phase maintain modes. When the frequency search is finished, the phase error between the reference clock and the feedback clock will approach to zero. So the proposed method can reduce the circuit complexity and locking time of a phase-locked loop system. The proposed ADPLL is implemented in UMC 90nm 1P9M standard CMOS technology with standard cell. The simulation results show that the output clock has a peak-to-peak jitter of 80ps, the power consumption is 46mW, the output frequency is 1.25GHz, and the chip size is 140um×110um.