新穎垂直通道薄膜電晶體之研究

Abstract

首先，我們製作與驗證新穎的對稱性垂直通道結構搭配鎳金屬矽化物之多晶矽薄膜電晶體。我們研究了鎳金屬矽化物、氨電漿處理時間與氧化層過蝕刻深度對此元件電性的影響。元件的導通電流可以藉由鎳金屬矽化物的技術來提升，因為鎳金屬矽化物的技術可以有效的降低串聯阻抗。在氨電漿處理時間對元件電性的影響方面，十分鐘的氨電漿處理跟其他較長時間的氨電漿處理相比有比較好的導通電流及比較低的漏電流。元件的漏電流與開關電流比可以藉由增加氧化層過蝕刻深度來改善與提高。另一方面，元件的漏電流也可藉由增加懸浮區的長度來改善。然而，串聯阻抗會隨著懸浮區的長度得增加而增加；因此懸浮區的長度並不能無限制的增長，懸浮區會有一個最佳化的長度。跟傳統的水平通道頂部閘極的多晶矽薄膜電晶體相比較，俱鎳金屬矽化物之對稱性垂直通道多晶矽薄膜電晶體多比較好的元件電性，包括較佳的次零界擺幅、較低的漏電流以及較高的場效載子遷移率。俱鎳金屬矽化物之對稱性垂直通道多晶矽薄膜電晶體其次零界擺幅皆低於315 mV/dec，場效載子遷移率皆高於67 cm2/V • s，並且其開關電流比皆大於十的八次方。 隨後，我們研究了閘極氧化層微縮情況下的鎳金屬矽化物之對稱性垂直通道多晶矽薄膜電晶體的元件特性，並且研究了此元件的可靠度；包括自我生成熱效應、熱載子效應與閘極正偏壓加壓測試。鎳金屬矽化物之對稱性垂直通道多晶矽薄膜電晶體在閘極氧化層較薄的條件下有較好的元件特性(尤其是次零界擺幅皆低於144 mV/dec)。同時，鎳金屬矽化物之對稱性垂直通道多晶矽薄膜電晶體在較薄的極氧化層、俱源汲極與閘極抵補區與較長的懸浮區的長度的情況下會有比較好的抑制汲極導致能障降低能力。鎳金屬矽化物之對稱性垂直通道多晶矽薄膜電晶體在較長的懸浮區的長度的情況下也會有比較好的抑制自我生成熱效應和熱載子效應能力。然而，鎳金屬矽化物之對稱性垂直通道多晶矽薄膜電晶體在較短的懸浮區的長度的情況下才會有比較好的抑制閘極正偏壓加壓測試能力。 除此之外，相較於自我生成熱效應和熱載子效應，閘極正偏壓加壓測試在偏壓小於4伏特的情況下將會元件的劣化的主要議題。也就是說，當所加的加強劣化測試偏壓不夠大到可以產生自我生成熱效應和熱載子效應的情況下，閘極正偏壓加壓測試將會主導元件的劣化。鎳金屬矽化物之對稱性垂直通道多晶矽薄膜電晶體在加強劣化測試的閘極偏壓小於一半的加強劣化測試的汲極偏壓的情形下會有最嚴重的熱載子效應；這和大多數的多晶矽薄膜電晶體類似。 接著，我們應用金屬誘發側向結晶來製做垂直通道多晶矽薄膜電晶體的薄膜通道並且研究垂直通道多晶矽薄膜電晶體的結晶過濾效應。並且比較鎳金屬誘發側向結晶和鎳金屬矽化物誘發側向結晶的差別。較窄的結晶過濾寬度的通道會有較好的晶粒結晶性與較低的晶粒及晶粒邊界缺陷；也因為如此，可以利用較窄的結晶過濾寬度來製作元件及提高元件的特性。鎳金屬誘發側向結晶和鎳金屬矽化物誘發側向結晶相比較的結果是它們兩者部沒有任何差別，這顯示鎳金屬矽化物誘發側向結晶並無法有效的降低鎳金屬在通道中的殘留。不過，這兩種結晶方的製作出的元件皆可利用通道數目的增加來提高開關電流比並起不會影響其他的元件特性。 最後，我們將無接面式電晶體元件的概念與垂直通道薄膜電晶體做結合。我們發現無接面式電晶體元件的通道厚度對於載子的傳輸而言是一個很重要的參數。因此要有良好的無接面式電晶體元件特性需要有一個最佳化的通道厚度。為了得到更好的無接面式垂直通道薄膜電晶體的元件特性，我們將雙閘極結構的概念應用到無接面式垂直通道薄膜電晶體上。在雙閘極的無接面式垂直通道薄膜電晶體上，我們也可以藉由鎳金屬矽化物的技術來提高元件的導通電流。此外，再升溫情況下的元件特性，其次零界擺幅、漏電流與導通電流皆會隨著溫度的升高而增加；臨界電壓則是會隨著溫度的升高而降低。

First, we have successfully fabricated and demonstrated the symmetric vertical-channel Ni-salicided polycrystalline silicon thin-film transistors (VSA-TFTs) for the first time. We investigate the device characteristics and effect of Ni-salicidation, NH3 plasma treatment time, and oxide overetching depth for VSA-TFTs. The on-state current may be improved by Ni-salicidation due to reduce the series resistance. The VSA-TFTs fabricated with 10-min NH3 plasma treatment time have lower off-state current and higher on-state current compared with others long NH3 plasma treatment time. The off-state current and on/off current ratio may be improved by increasing the oxide overetching depth. On the other hand, the off-state current may be improved by increasing the length of floating n+ region. The series resistance in the floating n+ region rises with increasing the length of floating n+ region, and therefore, the length of floating n+ region may not be indefinitely increased. In comparison with the conventional top gate horizontal channel TFTs, the VSA-TFTs has better performance in term of subthreshold swing, off-state current and field effect mobility. The VSA-TFTs display good subthreshold swing (below 315 mV/dec), steep mobility increase (field-effect mobility larger than 67 cm2/V • s), and large on/off current ratio of more than 108 (W/Lfloating =1/3 □m). Then, the characteristics of symmetric vertical channel Ni-salicided poly-Si thin-film transistors with gate oxide scaling are demonstrated. The reliability issues of VSA-TFTs, including SH stress, HC stress, and positive gate bias (PGB) stress are also investigated. The VSA-TFTs with thinner gate oxide thickness have better device performance (S.S. < 144 mV/dec). The VSA-TFTs with thinner gate oxide thickness, an offset structure, and a longer floating n+ region have better immunity to DIBL. VSA-TFTs with longer floating n+ region also have better immunity under hot carrier (HC) stress and self-heating (SH) stress. However, VSA-TFTs with a shorter floating n+ region have better immunity to positive gate bias (PGB) stress. In additional, the PGB stress, rather than SH stress or HC stress, becomes a major issue for VSA-TFTs under the stress bias below 4V. In other words, PGB stress will dominate the degradation behaviors when the stress bias is not high enough to achieve SH stress and HC stress. The worst degradation condition of VSA-TFTs under HC stress, similar to that of most TFT devices, occurs when the stress of VG is less than half of VD. Third, the characteristics of vertical channel poly-Si thin-film transistors fabricated by MILC with crystal filtering technique are demonstrated. We also compare several important device parameters of NILC-VTFTs with NSILC-VTFTs. The narrower crystal filtering width has better grain crystallization and less intra-grain and grain boundaries defects. Hence, the device performance will be improved by reducing the crystal filtering width. Comparison of NILC-VTFTs and NSILC-VTFTs, the method of NSILC can’t efficient reduce the Ni and NiSi2 precipitates concentration and improve the device performance. The on/off current ratio of NILC-VTFTs and NSILC-VTFTs can be improved by increasing the channel numbers. Finally, we combine the vertical-channel polycrystalline silicon thin-film transistors (VC-TFTs) with the junctionless concept. We find the channel film thickness is a very important factor in the carrier transport. Hence, it is important to trade off the channel film thickness to obtain optimum device characteristics. In order to improved gate to channel controllability, we combine junctionless vertical channel thin-film transistor with double-gate structure (called DGJL-VTFTs) and study its characteristics. In DGJL-VTFTs, it has better device performance under double-gate operation mode. In additional, the drain current can be improved by using Ni-salicidation technology. The threshold voltage decreases as temperature is increased. The subthreshold swing, off-state current and on-state current increase as temperature increases.