整合訊號矽穿孔與三維積體電路之全域繞線去改善線長與溢出

Abstract

三維積體電路使用訊號矽穿孔來連接不同層的晶片。適當地規劃訊號矽穿孔可以降低擁擠區域的個數、改善訊號的延遲且提昇電路的效能，而因為矽穿孔體積想當大，所以粗略的擺放訊號矽穿孔不止降低前一步驟使用擺放器所估算之線長準確度也嚴重影響電路的良率。這個研究整合訊號矽穿孔的擺置與全域繞線去降低插入訊號矽穿孔後對於電路的影響。我們所提出的方法主要包含兩個步驟：考慮擁擠區域之最初的訊號矽穿孔位置去擺放訊號矽穿孔到適當的位置與矽穿孔個數到任何需要的訊號矽穿孔的線路；在繞線階段利用重新擺置可移動的訊號矽穿孔去解決減少線長與降低溢出的問題。實驗數據結果說明我們提出的方法可以有效的降低繞線長度3 百分比到17 百分比且將低擁擠區域個數比其他現在發展科技中常使用的方法在三維擺放測試資料上。從Cadence SoC Encounter 的結果說明我們的訊號矽穿孔擺放結果也可以降低違反設計準則的個與線長2 百分比到10 百分比。

Signal Through-Silicon-Vias (STSVs) are employed to connect different dies in 3D-IC designs. Well-planned STSVs can reduce the number of congested regions and the signal delay and improve circuit performance, while ill-placed STSVs not only reduce the accuracy of estimation of wirelength by the placer but also seriously affect the circuit yield because TSVs are very large. This study integrates STSV-planning with global routing to eliminate the above side-effects of inserting STSVs. The proposed approach mainly comprises two steps: initial STSV positioning places STSVs in appropriate locations and STSV count to each net with the estimation of congested regions; then wirelength-minimization and overflow-reduction issues are addressed by replacing movable STSVs during global routing. Experimental results show that the proposed method effectively improves the total routed wirelength by 3%~17% and reduces the number of congested regions, below those obtained using state-of-the-art procedures based on 3D-placement benchmarks. Moreover, the results of planning can reduce the number of DRC violations and the wirelength by 2%~10%, below those of other methods from the reports of Cadence SoC Encounter.