無接腳積體電路可行性研究

Abstract

摘要

本論文研究無接腳積體電路(ZP-IC)的可行性。ZP-IC可以大量節省片面積，不受電源線束縛，不用更換電池，使用上更靈活，我們發現可以利用非晶矽太陽能電池/MIM電容/ASIC的結構解決電源的問題，並提出分壓電容順序放電、分壓電容並聯放電及動態分壓電容三種架構，以更有效率的使用電力。經電腦模擬我們確認所提出的架構可大幅增長工作時間。利用分壓電容放電的特性，我們更進一步提出全電容式變壓器的構想。最後，由研究結果顯示在製程上整合非晶矽太陽能電池、紅外線傳輸、ASIC是實現ZP-IC最可行的方案。

Abstract

This thesis studies the feasibility of Zero Pin Integrated Circuit (ZP-IC). ZP-IC, being unrestricted by the power cord, can substantially reduce chip area, and has no need to replace the battery. It is very flexible in practical applications. We find that the structure of amorphous silicon solar cells/MIM capacitor/ASIC is able to solve the power problem in ZP-IC. Three structures: the sequential discharge partial voltage capacitor, the parallel discharge partial voltage capacitor and the dynamic partial voltage capacitor are proposed, which can enable efficient use of electric power. By the simulation results, we make sure that the structures we proposed reach the expected performance, as the working time greatly lengthening. Furthermore, we propose the idea of All-capacitor transformer by taking advantage of the partial discharging capacitor. Finally, based on our study, we conclude that integrating amorphous silicon solar cells; IrDA and ASIC is the most promising scheme to realize the idea of ZP-IC.