THE ANALYSIS AND DESIGN OF CMOS MULTIDRAIN LOGIC AND STACKED MULTIDRAIN LOGIC

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DC 欄位	值	語言
dc.contributor.author	WU, CY	en_US
dc.contributor.author	WANG, JS	en_US
dc.contributor.author	TSAI, MK	en_US
dc.date.accessioned	2014-12-08T15:06:06Z	-
dc.date.available	2014-12-08T15:06:06Z	-
dc.date.issued	1987-02-01	en_US
dc.identifier.issn	0018-9200	en_US
dc.identifier.uri	http://hdl.handle.net/11536/4666	-
dc.language.iso	en_US	en_US
dc.title	THE ANALYSIS AND DESIGN OF CMOS MULTIDRAIN LOGIC AND STACKED MULTIDRAIN LOGIC	en_US
dc.type	Article	en_US
dc.identifier.journal	IEEE JOURNAL OF SOLID-STATE CIRCUITS	en_US
dc.citation.volume	22	en_US
dc.citation.issue	1	en_US
dc.citation.spage	47	en_US
dc.citation.epage	56	en_US
dc.contributor.department	電控工程研究所	zh_TW
dc.contributor.department	Institute of Electrical and Control Engineering	en_US
dc.identifier.wosnumber	WOS:A1987F877900007	-
dc.citation.woscount	5	-
顯示於類別：	期刊論文

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