在鍺通道金氧半場效電晶體上去釘札後蕭特基二極體以及n+/p二極體的研究

Abstract

此論文中，首先我們分析金屬/絕緣體/鍺二極體的接面特性，並且成功的利用二氧化鍺以及三氧化二鋁來緩解了費米能階釘札(Fermi-level pinning)的現象，並在p型鍺基板上達到相當高的電洞蕭特基能障(Schottky barrier for hole)。經過計算，在使用二氧化鍺的情況下,釘札係數(pinning factor)在p型與n型鍺基板上各是0.41和0.59。而在使用三氧化二鋁的情況下, 釘札係數在p型與n型鍺基板上各是0.347和0.495。其中,使用二氧化鍺當作去釘札層(depinning layer)會有比使用三氧化二鋁還要來的好的去釘札(depinning)效果；這是因為二氧化鍺與鍺的接面品質比三氧化二鋁的要來的高。再來，我們透過不同金屬的使用，發現了在金屬/n型鍺接面中加入一層二氧化鈦，可以使得原本的整流特性轉變成了歐米特性，而這原因是由於二氧化鈦有n型半導體的特性。 根據去釘札的蕭特基二極體的經驗，我們成功的利用二氧化鍺以及二氧化鈦來製作出金屬源汲極(metal S/D)的純鍺n型場效電晶體。在比較下，由於二氧化鈦與鍺之間有較低的導帶能帶差(conduction band offset)，以至於在小的汲集電壓下，利用二氧化鈦所製作的電晶體會比用二氧化鍺的有較好的電流特性。利用我們的實驗結果分析在傳統鍺n型場效電晶體中使用二氧化鈦接面層的優缺點。透過在n+鍺與金屬間加入一層二氧化鈦可以有效降低蕭特基能障，然而這層二氧化鈦也帶來了額外的電阻效應。而且隨元件尺寸的微縮，這額外的電阻效應將會更加嚴重。 最後，我們研究在不同離子佈植的劑量與不同的退火溫度下的鍺n+/p接面特性。總結來說，透過使用適當的離子佈植劑量(2×〖10〗^14 cm^(-2))可以讓我們得到淺的接面深度也可以減低來自於劑量增加所帶來額外的擴散(concentration- enhanced diffusion)。而根據我們在鍺n+/p接面的經驗，我們成功製作出通道長度500奈米的鍺n型場效電晶體。並且其有著良好源極電流開關比(1.67×〖10〗^5)以及很低的次臨界擺幅並且沒有明顯的汲極引致能障降低效應。

In this thesis, firstly, metal/insulator/Ge (MIS) junctions were fabricated and analyzed electrically. We successfully release the FLP both on n and p type Ge by inserting the interfacial layer of GeO2 and Al2O3, and make the high SHB for hole in p-Ge case. The pinning factor of GeO2 case is 0.41 for p-Ge and 0.59 for n-Ge, while in Al2O3 case the pinning factor is 0.347 for p-Ge and 0.495 for n-Ge. The effect of de-pinning by using GeO2 is better than one by using Al2O3, which resulting from the better quality of GeO2/Ge interface. By applying TiO2 as the interfacial layer to different metal contacts, we find that the reason of I-V characteristic changing from rectifying to ohmic by the insertion of TiO2 layer is due to the n type semiconductor-like characteristics of TiO2. Secondly, basing on the experiences in the de-pinned junctions, we successively demonstrate the device characteristics of the metal S/D Ge n-MOSFETs with GeO2 and TiO2 as depinning layer. Compared to GeO2, the smaller conduction band offset of TiO2 lead to the better drain current characteristic at low drain voltages. Furthermore, pros and cons of adding the TiO2 interfacial layer to the conventional Ge n-MOSFETs have been discussed according to our experimental data. The insertion of TiO2 layer at metal/n-Ge interface cannot only reduce the Schottky barrier height but also induce an additional resistance. As the channel length scaling down, the effect of additional resistance will be more serious. Finally, we investigate the characteristics of Ge n+/p junction with different implantation dosages and activation temperatures. It is concluded that medium implantation dosage (2×〖10〗^14 cm^(-2)) enables us to obtain the shallow junction and suppress the effect of concentration-enhanced diffusion. According to the experiences in n+/p junctions, the 500nm Gate-length n-MOSFET was achieved with high Ion/Ioff ration (1.67×〖10〗^5 for IS), low S.S, and no obvious DIBL.