適用於快閃記憶體之(9216,8195)拉丁方陣低密度奇偶校驗碼解碼器

Abstract

BCH碼因為硬體架構非常簡單而且只需要硬式輸入來解碼，目前是應用在快閃記憶體系統上錯誤更正碼的主流。雖然二位元軟式輸入被提出以加強錯誤更正能力。但二位元軟輸入對於BCH碼的錯誤更正能力並沒有很大的幫助。因此，本論文提出適用於快閃記憶體系統的低密度奇偶校驗碼（Low Density Parity Check,簡稱LDPC Codes）及其解碼器架構，以二位元軟輸入之LDPC Codes提供在相同編碼率下比BCH碼更好的錯誤更正能力。 我們使用拉丁方陣演算法建構出編碼率為0.89的(9216,8195) LDPC Codes，並利用Area-Efficient Column Shuffle Decoding架構來降低硬體複雜度，解碼過程 中從行的方向把奇偶校驗矩陣分割成36組，每一組再從列的方向分割為4個小組，這樣的架構能夠使檢查節點運算元被簡化為一個三對二的排序器。另外，我 們利用加權平均數的概念來達到二位元軟輸入之最佳化，在信噪比(Signal to Noise Ratio) 5.0dB的情況下，我們所提出的LDPC Code位元錯誤率為10−9，然而具有73個錯誤更正能力的BCH碼在此情況下的位元錯誤率為10−2。使用UMC 90nm製程，所提出的解碼器邏輯閘數約為605.3k，在4次遞代解碼次數的情況 下，可達到 1.58Gb/s 吞吐量。

BCH code is mainly adopted in NAND flash memory system because of its simple hardware architecture for hard input requirement. Although soft input can be considered to improve the correcting capability, BCH code has little improvement when soft input is provided. In this thesis, a 2-bit soft input LDPC decoder is presented to outperform BCH code under same code rate. The (9216, 8195) LDPC code with code rate 0.89 is constructed from Latin square algorithm. An Area-Efficient Column Shuffled decoding architecture is proposed to reduce hardware complexity. Columns in parity-check matrix are divided into 36 groups, and all the rows of each column group are divided into 4 subgroups. Following this architecture, a check node update unit can be simplified as a 3-to-2 sorter. In addition, the concept of weighted mean is applied to optimize 2-bit soft input quantization. At signal to noise ratio (SNR) of 5.0dB, bit error rate (BER) of our proposed LDPC code is 10−9 whereas BCH code that can correct 73 errors is 10−2. Using 90nm CMOS technology, our design with 605.3k equivalent gates can achieve the maximum throughput 1.58 Gb/s under 4 decoding iterations.