低壓高速動態比較器之實現

Abstract

本論文設計兩種低壓高速動態比較器，針對核心電路“栓鎖器”做改善，使比較器在低供給電壓操作時時，讓比較器能有足夠得過驅動電壓，保持足夠的轉導，維持高速的運作，並使用65nm CMOS做驗證，使之能夠在0.6伏特時，操作速度然能夠達到GHz的等級。第一個比較器在供給電壓0.6V時，操作速度可達1GHz，偏差電壓(1σ) 為6mV，雜訊大小(1σ)為0.65mV，敏感度僅需3mV即可達到BER=10-9，同時功率消耗僅38μW。第二個比較器在供給電壓0.6V時，操作速度更可高達1.3GHz，偏差電壓(1σ) 為7.5mV，雜訊大小(1σ)為0.5mV，敏感度僅需4.2mV即可達到BER=10-9，同時功率消耗僅64μW。

This thesis presents two low voltage, high speed dynamic comparators. It improves the core circuit “latch architecture”, so the comparators can operate at low supply voltage. The comparators have the large enough overdrive voltage to keep the transconductance, so the comparators can maintain the high speed operation.And realizing comparators in 65nm CMOS. The first comparator operate at supply voltage is 0.6V, the operating speed is 1GHz, and the input referred offset(1􀍚) is 6mV, the input referred noise(1􀍚) is 0.65mV, and the sensitivity is 3mV to achieve the BER is 10-9. And the power consumption is only 38􀊅W. The second comparator operate at supply voltage is 0.6V, the operating speed is 1.3GHz, and the input referred offset(1􀍚) is 7.5mV, the input referred noise(1􀍚) is 0.5mV, and the sensitivity is 4.2mV to achieve the BER is 10-9. And the power consumption is 64􀊅W.