研發微電阻銲接與矽晶圓穿孔製程?應用於微系統封裝技術

Abstract

本論文利用電阻銲接的概念，將其應用於電子/微機電系統構裝技術上。其作法是在一晶圓上設計「接合環」（bonding ring）與TSV（Through Silicon Via）等金屬結構；在另一片設計晶圓上的金屬電極分佈，設計另一片晶圓上的金屬電極分佈，使得當這兩片晶圓相接合時，發生金屬/金屬接觸。由於金屬/金屬接觸面的接觸電阻高，因此可利用電阻銲接來做局部加熱接合環結構的金屬/金屬接觸面以及TSV結構的金屬/金屬接觸面，進而進行瞬間液相(TLP, Transient Liquid Phase)接合。透過接合環的接合可以完成兩片晶圓的氣密性接合；透過TSV的接合可以完成IC電路與MEMS元件電性的連結。接合環與TSV的接合可以設計成同時完成或是分開完成，待二者的接合完成後即完成了電子/微機電系統的封裝。惟若要同時完成氣密接合與IC-MEMS元件電性連結，在接合前接合環與TSV必須藉由金屬導線的定義使之連結成電路的串聯模式，在接合完成後，必須重新定義金屬導線，將接合環與TSV的電性分開，或是將不同的TSV之間的電性分開。 本論文研發此新技術的優點是：（1）接合金屬的接觸面不需要平坦化、去氧化層、等特別處理。（2）本作法屬於局部加熱，因此局部的接合溫度可以較高而不會損壞IC電路或是MEMS元件，所以接合金屬的選擇更具多樣性。（3）本作法利用局部加熱方式進行接合，但是不需要在晶圓上製作微加熱器，可以節省晶圓面積。（4）本作法可進行晶圓層級的封裝，且封裝完成後的電性輸入╱輸出點皆在晶圓的外露面，因此可以進行晶圓層級的測試。 而本研究也重工在兩晶圓試片分別電鍍有Ni(5 μm)/Sn(3 μm) 作為環狀接合結構，在兩互相對準加壓後，透過TSV垂直式導線輸入固定電壓3.5V，電流變化介於4~2A，在維持加熱1hr後可成功以局部加熱的方式進行瞬間液相接合，等待試片冷卻後，進而完成封裝，證實此封裝方式的可行性。

This paper proposes a novel wafer level packaging for integrated circuits (IC) and microelectromechanical system (MEMS) devices. In this method, two wafers were bounded by resistance welding with simultaneously through-silicon-via (TSV) connection and cavity sealing. In general, bonding techniques require two bonding surfaces to be flat to have intimate contact for bonding. If the surface is rough, it needs to be conditioned. Otherwise, the bonding temperature needs to be high to soften the bonding material, which could damage the device materials such as aluminum in circuits. In a word, the surface roughness of the bonding surface is not preferred and extra care/cost should be paid for that. The proposed IC-MEMS packaging method has the following advantages. First, it does not require flat surface for bonding. Instead, it makes use of the surface roughness of TSV for resistance welding, which achieves transient liquid phase (TLP) for wafer bonding. Second, it is a local heating process but does not require pre-patterned micro-heaters. Thus, high-temperature bonding materials can be used for better bonding properties and no extra area is needed for the deployment of micro-heaters. Third, it can achieve wafer-level testing. This fabrication/bonding process is briefly described as follows. The thickness of bottom wafer is 525 □m and formed through wafer trenches. The TSV is formed by the Nickel electroplating which completely refilled those trenches and is used as an electrical interconnect between two sides of the bottom wafer. Both on the top and bottom wafers, 5□m-Ni /2□m-Sn standouts are created and patterned as a bonding ring for bonding two wafers together later on. Note that, those Ni/Sn films can be fabricated by cheap fabrication processes because the surface roughness is not critical. After that, two wafers are brought together and a constant voltage is applied to two contact pads, which can be accessed at the bottom side of the bottom wafer. The surface roughness introduces a large contact resistance to the circuit and completes the current loop. Thus, it creates a local heater at contact points. When the temperature of these contact points reach 300℃, the Ni-Sn TLP bonding happens, which seals the gap for bonding two wafers together and complete the electrical interconnects between two wafers simultaneously. The Ni-Sn bonding took place at several contact points but many voids existed. The existence of voids was likely because we did not operate this bonding process under vacuum. More experiments are on the way to calibrate the performance of this fabrication process.