A NEW ANALYTICAL 3-DIMENSIONAL MODEL FOR SUBSTRATE RESISTANCE IN CMOS LATCHUP STRUCTURES

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DC Field	Value	Language
dc.contributor.author	CHEN, MJ	en_US
dc.contributor.author	WU, CY	en_US
dc.date.accessioned	2014-12-08T15:06:11Z	-
dc.date.available	2014-12-08T15:06:11Z	-
dc.date.issued	1986-04-01	en_US
dc.identifier.issn	0018-9383	en_US
dc.identifier.uri	http://hdl.handle.net/11536/4757	-
dc.language.iso	en_US	en_US
dc.title	A NEW ANALYTICAL 3-DIMENSIONAL MODEL FOR SUBSTRATE RESISTANCE IN CMOS LATCHUP STRUCTURES	en_US
dc.type	Article	en_US
dc.identifier.journal	IEEE TRANSACTIONS ON ELECTRON DEVICES	en_US
dc.citation.volume	33	en_US
dc.citation.issue	4	en_US
dc.citation.spage	489	en_US
dc.citation.epage	493	en_US
dc.contributor.department	交大名義發表	zh_TW
dc.contributor.department	工學院	zh_TW
dc.contributor.department	National Chiao Tung University	en_US
dc.contributor.department	College of Engineering	en_US
dc.identifier.wosnumber	WOS:A1986A587400009	-
dc.citation.woscount	2	-
Appears in Collections:	Articles

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