對基於寫入資料決定之操作輔助技術的靜態隨機存取記憶體進行開路缺陷之測試與分析比較

Abstract

隨著科技的進步，記憶體所佔的面積越來越大，其耗能也變得值得重視。由於低耗能的需求，許多研究已經致力於開發可以在低電壓下操作，且維持良好表現的新靜態隨機存取記憶體。新型記憶體有著新的結構與設計技巧，因此可能會有有別於傳統靜態隨機存取記憶體的錯誤行為，而需要特殊的測試方式來測試這些錯誤模型。在本篇論文中，我們主要著重在測試新型設計中的低電壓對基於寫入資料決定之操作輔助技術的靜態隨機存取記憶體的開路缺陷。這個新型的記憶體協調操作兩條寫入字線與寫入資料決定之動態電壓電路以達成寫入動作，而以一條獨立的讀取道路完成讀取。以此特殊的結構為基準，我們提出了一個稱為自我迴路攻擊的測試方式。這個測試方式能夠測量到對於此種靜態隨機存取記憶體與寫入資料決定之動態電壓電路，過去的測試方法沒辦法偵測到的錯誤。此外，這個方法能更進一步的以較少的時間完成測試。

As technology improves, the occupation area of memory becomes larger, and power consumption of memory is considerable. Due to the lower-power demand, a lot research effort has been devoted to develop new SRAM cell designs that can be operated at low VMIN but with high performance. The new SRAM cell design has its own cell structure and design techniques, which may result in different faulty behaviors than the conventional 6T SRAM and require specialized test methods to detect uncovered fault models. In this thesis, we focus on testing the open defects of a new low-VMIN data-aware dynamic-supply 8T SRAM design. The new SRAM utilizes two write word-lines cooperating a data aware dynamic-supply circuitry for write and an independent path for read. Based on the specific structure, we propose a novel test method called self-loop attacking (SLA). The proposed method detects all the undetected defects of traditional tests no matter in the SRAM cell or in the data-aware dynamic-supply circuitry. Moreover, it can further complete the detection with much less test time.