五十億級資料傳輸室內無線SC/OFDM接收機之系統架構設計與FPGA實作

Abstract

本論文提出針對IEEE 802.15.3c標準設計與實作之單載波(SC)和正交多頻分工(OFDM)雙模無線基頻接收機。本無線基頻接收機含前置碼(preamble)/符元(symbol)邊界偵測、取樣時脈飄移同步估測補償、載波頻率漂移同步估測補償、時域等化器以及相位雜訊消除等五個主要功能性電路區塊。本論文將關鍵之模組為兩種模式所共用以達節省硬體複雜度之目的。 此無線基頻接收機使用運算元阻隔、時脈訊號閘控以及記憶體共用三種低功耗電路設計技術。首先，應用運算元阻隔技術節省整體36.3％之功耗。接著使用時脈訊號閘控技術降低9.07％之功耗。最後藉由記憶體共用技巧再縮減了30.83％之功耗。整體而言，應用此三種低功耗電路設計技術共節省59.94％總功耗。硬體合成使用了65奈米1伏特1P9M CMOS製程，操作頻率為333MHz，資料傳輸率在單載波和正交分頻多工模式中，分別可達到3.52Gbps和5.28Gbps，等效邏輯閘數為250萬個，總功耗為0.91瓦，未具有任何編碼保護下的位元錯誤率在單載波和正交分頻多工模式中，分別可達到7.36×10-5 和9.30×10-6 。 最後，本論文將此無線基頻接收機電路以可程式邏輯閘陣列（FPGA）方式實現，此次實作使用的可程式邏輯閘陣列晶片為Xilinx Virtex-5 LX 330。本論文中建立了整套可程式邏輯閘陣列實現流程。無線基頻接收機電路使用了Virtex-5 LX 330之89％程式塊(Slice)、98％嵌入式區塊RAM(Block RAM)、100％數位訊號處理單元(DSP48E)硬體資源。

This thesis proposes a single carrier (SC) and high speed interface (HSI) dual mode wireless receiver which is designed and implemented for IEEE 802.15.3c standard. There are five main block functional blocks in the baseband receiver: boundary detector, sampling clock offset (SCO) cancellation, carrier frequency offset (CFO) cancellation, time domain equalizer, and phase noise cancellation. The hardware of key modules between SC/HSI modes is shared to reduce hardware complexity. Operand isolation, clock gating, and memory sharing are applied in this wireless baseband receiver to reduce the power consumption. First, by applying the operand isolation technique, the power is reduced by 36.30 %. Second, 9.07 % of power is saved by adding integrated clock gating (ICG) cell to do clock gating. Third, memory used by BD, EQ, PNC, and FFT are merged so that it can reduce another 30.83 % of power. In conclusion, the total power of proposed WPAN baseband inner receiver is decreased by 59.94 %. The circuit is synthesized by 65 nm 1P9M CMOS process with supply voltage of 1 V. The clock rate can achieve 333 MHz. The data rate can achieve 3.52 Gbps and 5.28 Gbps in SC and OFDM mode, respectively. The equivalent gate count is 2504.62 K and the power consumption is 0.91 W. Without channel coding, the BER can achieve 7.36×10-5 and 9.30×10-6 in SC and OFDM mode, respectively. Finally, the proposed wireless baseband receiver is implemented by FPGA, Xilinx Virtex-5 LX 330. A flow of FPGA prototyping has been set up. The wireless baseband receiver design occupies 89 % slices, 98 % block memory, and 100 % DSP48E of Virtex-5 LX 330.