應用於時脈產生器之全客戶式全數位鎖相迴路

Abstract

在科技日新月異下，所有產品電子化、積體化已是必然過程，面對電子電路全面System On Chip，不論是通訊領域上傳遞訊號所需穩定載波的需求；或是晶片內介於各運作方塊間的時脈而言，一個穩定的頻率震盪器已無法滿足需求。相位資訊也不可避免地被萃取出並進行各方面的應用，因此有了鎖相迴路的蓬勃發展。鎖相迴路最初是以類比式設計為主，現今在通訊的重要應用上幾乎完全使用類比式鎖相迴路，但由於製程不斷更新，每替換一次製程，類比式鎖相迴路的設計就必須從頭來過，研發所消耗的時間過長；加上類比式濾波器極占面積，基於產學界節省成本需求強烈下，全數位式鎖相迴路在近十年來迅速成為熱門研究主題。低功耗、面積小以及鎖定速度快是其優點；而在鎖定後的相位表現上要超越類比式鎖相迴路，則有待突破。 在本篇論文中，我們將提出一套全客戶式設計全數位式鎖相迴路的流程，將其應用於時脈產生器上；並提出全對稱式架構與雙層次的時間數位轉換電路作為量測相位誤差之用，在第一顆晶片中採用週期限性的數位控制震盪器，震盪頻率為282MHz~524MHz；第二顆晶片則採用電流拉扯式的頻率線性架構，震盪頻率則落在242MHz~1.18GHz。第一顆晶片將頻率鎖定至400MHz；第二顆晶片則將頻率鎖定於800MHz。而作為時脈產生器，時脈抖動是主要指標；在第一顆晶片量測到7.45ps的方均根時間抖動(rms jitter)，41.22ps的峰對峰值時間抖動(Peak to Peak jitter)。而在第二顆晶片的後模擬中呈現2.86ps的方均根時間抖動， 21.11ps的峰對峰值時間抖動。面積上第一顆晶片核心面積為0.26 ，第二顆晶片核心面積為0.295 ；功率消耗上第一顆晶片約為7.55mW，第二顆晶片約為14.55mW。

In recent years, the advance of technology goes so fast that almost every product becomes electronic and integration is a necessary process. With the progress of electronics and circuits to become System On Chip, no matter for either a stable carrier used for communication applications or a clock signal between operating blocks in the chip, a stable frequency oscillator does not satisfy the above needs. Phase information is usually extracted for many applications. That is why the advance of the phase-locked loop(PLL) grows fast. In the beginning, PLL design is realized by analog form, and it has been used in many communication applications. However, along with the progress of process technology, the circuit needs to be re-designed whenever the process updates, which takes much time. On the other hand, the analog filter occupies lots of area. With the cost-down concern stronger than any other conditions, an All-Digital PLL becomes a hot topic around the world in the past decade. Low power consumption, small area, and fast locking time are the main advantages; but after locked, the reference spur performance is poorer than its analog form, so there would require a breakthrough to solve the issue. In this reserch, we provide a novel approach of constructing an All-Digital Phase Locked Loop by Full-Custom form, targeted for clock generator applications. We also propose an all symmetric three-step and Two-Level Time-to-Digital Converter for phase error measurement. The first chip has a linearly periodic structure of Digitally-Controlled Oscillator with operation range from 282MHz to 524MHz; the second chip has a current-starving Linear-frequency structure with operation range from 242MHz to 1.18GHz. The first chip is locked on 400MHz, the second one is locked on 800MHz. Time jitter is an important indicator of a clock generator. The first chip has 7.45ps rms jitter and 41.22ps peak-to-peak jitter while the second chip has post-simulation results of 2.86ps rms jitter and 21.11ps peak-to-peak jitter.