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dc.contributor.authorYu, Shao-Mingen_US
dc.contributor.authorLee, Jam-Wenen_US
dc.contributor.authorLi, Yimingen_US
dc.date.accessioned2014-12-08T15:06:44Z-
dc.date.available2014-12-08T15:06:44Z-
dc.date.issued2007-02-01en_US
dc.identifier.issn0167-9317en_US
dc.identifier.urihttp://dx.doi.org/10.1016/j.mee.2006.02.006en_US
dc.identifier.urihttp://hdl.handle.net/11536/5290-
dc.description.abstractIn this paper we propose a silicide design consideration for electrostatic discharge (ESD) protection in nanoscale CMOS devices. According to our practical implementation, it is found that a comprehensive silicide optimization can be achieved on the gate, drain, and source sides with very few testkey designs. Our study shows that there is a high characteristic efficiency for various conditions in particular, for optimizing the performance of sub-100 nm complementary metal-oxide-semiconductor devices in system-on-a-chip era. (c) 2006 Elsevier B.V. All rights reserved.en_US
dc.language.isoen_USen_US
dc.subjectelectrostatic dischargeen_US
dc.subjectsilicideen_US
dc.subjectnanoscale deviceen_US
dc.subjectVLSI circuiten_US
dc.subjectsystem-on-a-chipen_US
dc.subjectmodelingen_US
dc.subjectsimulationen_US
dc.subjectoptimizationen_US
dc.titleAn optimal silicidation technique for electrostatic discharge protection sub-100 nm CMOS devices in VLSI circuiten_US
dc.typeArticle; Proceedings Paperen_US
dc.identifier.doi10.1016/j.mee.2006.02.006en_US
dc.identifier.journalMICROELECTRONIC ENGINEERINGen_US
dc.citation.volume84en_US
dc.citation.issue2en_US
dc.citation.spage213en_US
dc.citation.epage217en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.department電信工程研究所zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.contributor.departmentInstitute of Communications Engineeringen_US
dc.identifier.wosnumberWOS:000244383000004-
Appears in Collections:Conferences Paper


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