完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | 鄭元更 | en_US |
dc.contributor.author | Yuan-Geng Cheng | en_US |
dc.contributor.author | 鄭恩澤; 吳錦川 | en_US |
dc.contributor.author | En-Jer Jang; Jiin-Chuan Wu | en_US |
dc.date.accessioned | 2014-12-12T02:10:38Z | - |
dc.date.available | 2014-12-12T02:10:38Z | - |
dc.date.issued | 1992 | en_US |
dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#NT810430016 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/56873 | - |
dc.description.abstract | 於本論文中,吾人敘述一種低電壓、高速度,以互補式金氧半導體積體電 路技術所設計之可程式化除頻器。此可程式化除頻器可做為一般商用頻率 合成器積體電路之核心電路,蓋因商用頻率合成器積體電路之速度限制及 功率消耗均由其可程式化除頻器決定。吾人設計出一種新的'除完'偵測流 程技術及一種改良之往下數計數器,應用這些技術可以將傳統之可程式化 除頻器之速度提升至原來之三倍。又因吾人設計之此一可程式化除頻器乃 工作於1.35伏特之極低電壓,因此低電壓工作之電路設計所應注意之事項 亦有所探討。吾人並設計一種簡單且新穎之'狀態保留間歇工作鎖住迴路' 技術,此種技術可大幅改善分時多工之數位通訊產品之功率消耗,因此極 有可能成為未來商用頻率合成器積體電路中不可或缺之一部份。由HSPICE 所做電路模擬之結果可知,此可程式化除頻器在工作電壓僅1.35伏特且輸 入為僅0.25伏特振幅之正弦波時,最高工作頻率可達到 115百萬赫茲,此 時所消耗之功率僅0.5毫瓦。此可程式化除頻器為一具有19位元之可程式 化除頻器,其除數可為3至524287間之任一整數。此除頻器可用來設計供 一些可攜式無線電通信產品如呼叫器、無線電話、隨身收音機、電視機用 之頻率合成器,原本使用較笨重的3伏特或6伏特電池的這些產品將有機會 可以改用單一的1.5伏特電池且擁有更長的使用時間。 This thesis deals with the design of a low voltage, high speed CMOS programmable frequency counter design. It is the heart of a frequency synthesizer IC because the speed limitation and power consumption of the IC are both depend on the performance of the programmable frequency counter. By using a newly developed end-of-count (EOC) detecting algorithm and a modified ripple down counter, the speed of the new programmable frequency counter is almost three times fast when compared with the conventional one. Because this counter is designed to operate at only 1.35V, consideration about low voltage operation is discussed. A newly designed state- preserving intermittently locked loop (SPILL) technique is introduced, also. This technique can greatly improve the power saving efficient in Time-Division-Multiplexing (TDM) digital radio communication system and wil be widely adapted in the future. From the HSPICE simulation results, the counter can operate at 115MHz with 1.35V power supply voltage, the input signal is only 0.5V peak to peak sine wave and the power dissipation is only 0.5mW. The counter is a 19 bits programmable counter. The programming value N can be 3 to 524287. It can be used to design frequency synthesizer ICs for portable radio communication products such as pager, cordless phone, and portable FM and TV receiver. The portable radio communication products that use these frequency synthseizer ICs can use just one 1.5V battery to replace the heavier 3V or 6V battery and have longer operating time. | zh_TW |
dc.language.iso | en_US | en_US |
dc.subject | 頻率合成器; 除頻器; 相位鎖住迴路; 狀態保留間歇工作鎖住迴路; 除完偵測器 | zh_TW |
dc.subject | frequency synthesizer; frequency counter; phase locked loop; end-of-count detector | en_US |
dc.title | 低電壓高速度CMOS頻率合成器用之可程式化除頻器設計 | zh_TW |
dc.title | A Low Voltage,High speed COMS Programmable Counter Design for Frequency Synthesizer | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 電子研究所 | zh_TW |
顯示於類別: | 畢業論文 |