超大型積體電路用之複晶矽側壁之研究

Abstract

本論文針對不同的改良式之TEOS及Poly-Si側壁的電性與可靠性做了有系 統的研究.首先,各種不同的側壁材料包括TEOS ,LP Si3N4 , PE oxide ,BPSG 及Poly-Si.實驗結果顯示Poly-Si具有較高的介電常數 (K=11.9). 故展現了相當好的熱載子效應免疫力o其次,針對TEOS及Poly-Si側壁的加 強蝕刻做研究,此乃本實驗精神之所在o利用活性離子,如砷及硼對各種不 同的Poly-Si及TEOS厚度之穿透能力來評估取代LDD的可能性o當Poly-Si的 加強蝕刻之時間為50秒及 60秒,可達到LDD N-MOS的熱載子效應之免疫力o 唯其加強蝕刻時間較久 ,且硼離子由於原子量小及隨著後續的高溫(950 C)離子植入,造成了 P-MOS變成了空乏型的o At first ,different materials, including low pressure chemical vapor deposition (LPCVD) TEOS ,LP Si3N4 , plasma enhanced CVD (PECVD) oxide ,LPCVD borophosphosilicate glass (BPSG) and LPCVD Poly-Si ,have been systematically fabricated and the spacers for the VLSI circuits.The electrical properties shows that the Poly-Si is the best one of all the these spacers due to its highest dielectric constant ,K=11.9 , This result is consistent with the literatures.Although Si3N4 has the higher dielectric constant ,it encounters the stress problems so that it is not suitable for the practical application. BPSG and PE oxide are also excluded due to their impurity contents. Hence the remained two candidates ,TEOS and Poly-Si ,are further appraised in the second section of this study. The purpose of the second section is focused on the TEOS and Poly-Si spacers. By using TEOS and Poly-Si as the spacers with different over etching (O/E) times ,lightly doped drain (LDD) structures can be fabricated via the direct implantation of arsenic and boron ions through these spacers. Then ,this simplified LDD technology is evaluated to subsitute the conventional LDD process. Fortunely ,Poly-Si spacers with the O/E times of 50 sec and 60 sec can meet the requirement of hot carrier immunity comparable to that of the conventional N-MOS LDD devices. However ,too long O/E time of the Poly-Si spacers results in the deep penetration of the boron and cause the sub-micron P- MOS punch through after the high-temperature annealing at 950 C. Consequently ,the sub-micron PMOS with this Poly-Si spacer will exhibit the normal-on characterics.