1.2 V CMOS 類比數位轉換器

Abstract

為了結合電池驅動的運用於可攜式的環境中，很多用來降低工作電壓和減 少功率消耗的 CMOS 混合態電路技術被提出。我們提出了一個低電壓類比 信號處理系統。包含了全差動的結構和單晶的高電壓產生器。此架構能加 倍信號的動態範圍，以及能夠抑制雜訊的效應。依據此架構，且結合了許 多低電壓電路設計的技巧，一個 1.2V 的循環式類比數位轉換器已經被發 展出來。它是由兩個運算放大器，一個比較器和一些開關及電容所組成。 此類比數位轉換器具有對電容比值及放大器補偏電壓不敏感的特性，而其 主要的誤差源是來自於運算放大器的有限增益，及開關的電荷放射。一個 實驗用的樣本晶片已經利用了 0.8微米的N-well CMOS 製程實際製造出來 。在 8 kHz的取樣速度下，它可達到 8位元的解析度，而整個晶片的大小 是12m㎡。 Motivated by emerging battery-operated applications in portable environment, techniques are proposed which reduced supply voltage and power consumption in CMOS mixed-mode circuits. We proposed a low voltage analog signal processing system with fully differential topology and on-chip high voltage generation. It would double the dynamic range and reduce the noise effect. With this framework, a cyclic analog- to-digital converter with 1.2 V supply voltage has been developed associated with the design techniques for low voltage. It consists of two operational amplifiers, one comparator, switches and capacitors. The conversion characteristics are inherently insensitive both to capacitor ratio and to amplifier offset voltage, and the major error is from the finite gain of operational amplifier and the switch charge injection. An experimental prototype chip has been fabricated with a 0.8μm N- well CMOS process. It achieves an 8-bit resolution at a sampling rate of 8 kHz, and the chip area measures 12 m㎡.